The solid-state electronics industry faces relentless pressure to improve performance, increase functionality, decrease costs, and reduce design and development time. As a result, device feature sizes are now in the nanometer scale range and design life cycles have decreased to fewer than five years. Until recently, semiconductor device lifetimes could be measured in decades, which was essentially infinite with respect to their required service lives. It was, therefore, not critical to quantify the device lifetimes exactly, or even to understand them completely. For avionics, medical, military, and even telecommunications applications, it was reasonable to assume that all devices would have constant and relatively low failure rates throughout the life of the system; this assumption was built into the design, as well as reliability and safety analysis processes.
With technology evolution on the electronics industry to reduce transistor size and decrease cost while increasing transistor count per chip, however, runs counter to the needs of most high reliability applications where long life with exceptional reliability is critical and the supply voltage does not scale at the same pace, leading to higher current densities (which also produce higher temperatures). Transistors consist of lower number of atoms, such atoms may be displaced due to the stress caused by high temperature, frequency and current, leading to failures. As design rules have become tighter, power consumption has increased and voltage margins have become almost nonexistent for the designed performance level. In achieving the desired
performance levels, the lifetime of most commercial parts is the ultimate casualty. Most large systems are built with the assumption that electronic components will last for decades without failure. However, counter to this assumption, device reliability physics is becoming so well understood that manufacturing foundries are designing microcircuits for a three- to seven-year
useful life, as that is what most of the industry seeks. The military, aerospace, medical, and especially the telecommunications industries cannot afford to depend on custom parts for their most sophisticated circuit designs.
NBTI (negative bias temperature instability) is one of the most important sources of failure affecting transistors. NBTI degrades PMOS transistors whenever the voltage at the gate is negative (logic input "0"). The main consequence is a reduction in the maximum operating frequency and an increase in the minimum supply voltage of storage structures to cope for the degradation.
The increased current density and temperature accelerate device degradation,and thus, shorten the lifetime of the product. Moreover, the size of the chip does not scale, which implies that in every technology generation there is a larger number of such highly vulnerable devices.
The increasing electric field and temperature make negative bias temperature instability (NBTI) emerge as a threat for future technologies. NBTI affects PMOS transistors when negative voltage is applied at the gate (logic input "0"), causing an increase in the threshold voltage, and hence, a lower speed of the transistor. Many PMOS transistors affected by NBTI can be found in both
combinational and storage blocks since they observe a "0" at their gates most of the time.
Design of any digital circuit is based on the presumption that transistor parameters will remain bounded by a certain margin (typically ±15%) during the projected lifetime of the IC. This margin consists of initial manufacturing tolerance encapsulated in CPK numbers as well as other time-dependent parameter shifts due to various transistor degradation mechanisms like Hot Carrier Degradation (HCI), Gate Dielectric Breakdown (TDDB), Negative Bias Temperature Instability (NBTI), etc. Among them, NBTI has been a persistent (and perhaps most significant) reliability concern for CMOS technology generations below 130 nm node. Two factors - increasing oxide field (to enhance transistor performance without scaling gate oxide) and the use of oxynitrides (to prevent Boron penetration and to reduce gate leakage) appear to have exacerbated this PMOS-specific reliability issue. Specifically, NBTI causes systematic reduction in transistor parameters (e.g., drain current,transconductance, threshold voltage, capacitance, etc.) when a PMOSFET is biased in inversion (VS=VD=VB=VDD and VG=0). Since this NBTI-specific biasing condition arises universally in inverting logic, SRAM cells, I/O system,dynamic logic, etc., it is not surprising that the concern about NBTI is pervasive in the semiconductor industry.
Parameters that have an effect on NBTI,
