Abstract-Nanoelectronics is concerned with the application of nanotechnology on various electronic components particularly transistors. As nanotechnology is the study of matter on a nanoscale (atomic or molecular scale), nanoelectronics is generally referred to as the study of electronic devices built with components on the scale of nanometers (10−9 m). Nanoelectronics is debated as a disruptive technology since it is significantly different from the traditional electronic techniques. This nanoscale electronic technology holds promise for the future of electronics engineering.
The areas of advancements in nanoelectronics include molecular electronics and nanolithography. Molecular electronics is visualized as a potential way to assemble a large quantity of nanoscale objects such as nanotubes or nanowires to configure new electronic devices and circuit architectures. It is considered as an approach to significantly cut down the cost of fabrication, energy computations etc., as compared to the present semiconductor technologies. Furthermore, molecular electronics is a branch of nanoelectronics with so many prominent scopes and applications to probe into or investigate. Other approaches in the field of nanoelectronics include applications such as nanorobots and conductive polymers. This paper brings in the concept of nanoelectronics and the major advances in the field of nanoelectronics.
INTRODUCTION
Today, nanotechnology has become a technological sector of predominant importance. It deals with every aspect of nanoscale science and its application from a multidisciplinary perspective. Nanoscale is recogonized as the dimensions in the range of one-billionth of a meter, which is mathematically denoted as 10−9 m [1, 2]. Nanotechnology is not only concerned with reducing the size of devices but also constitute unique physical and chemical device properties. Nanoelectronics are an important branch of nanotechnology.
The use of nanoelectronics is booming in the field of engineering as it concerns with controlling matter in nanoscale. Leading edge CMOS technologies that are widely being handled in the present day are specific examples of nanoscale engineering at industrial level. Nanoelectronics constitute a wide range of applications at the nanoscale such as molecular materials and other nanodevices which in turn requires equipments for analyzing and tehniques for nanoscale fabrication and measurement [3]. The current attempts for developing nanoelectronic devices at nanoscale is aimed primarily by the limitation of active photolithography employed in fabricating devices of silicon, and also from the thought that , to verify Moore's law one has to look for answers at molecular level [4]. The ever increasing emphasis on changing price-performance ratio in the field of electronics continuously forces the electronics industries to enhance cost efficiency. The industrialists have depended on the extended scaling down of electronic devices such as transistor size to attain exponential increase in transistor counts, but this scaling is soon going to end. The main obstacles that stand in between are: the rapidly growing expenditure of fabrication, the limitations of lithography, and the size of the electronic devices. Consider the present day examples such as the parts of the electrical devices that are available in the market today has a thickness in the range of molecular scale and will still diminish as scaling goes on. Hence , when this scaling goes on and the size of the devices reach in the range of 1-2 atoms thick, the scaling will terminate and another methodology will have to be adopted. The most suitable successor to these conventional integrated circuits is molecular electronics and nanoscale devices [5, 6].
MOLECULAR ELECTRONICS
Molecular electronics is considered as the future of science and technology as it is inherently multidisciplinary in nature. The current trends for possible scenario of molecular electronics are classified into two different types of approaches: the top-down approach and the bottom-up approach. The top-down approach is similar to the one that is being followed by the standard microelectronics as well the later approach is attained from a nanotechnology chemistry based point of view.
The main differences between both these approaches, top-down and bottom-up respectively includes: (1) switching and programmability requirements at the smallest levels, (2) assembly of components in top-down is tenderly deterministic compared to random assembly in bottom-up approach, (3) one comprises of three terminal active devices on the other hand the later approach comprises of two-terminal active devices, (4) top-down has pre-designed gain on the contrary bottom-up has randomly generated gain [7]. "The top-down approach is defined as the generation of nanomaterials from the bulk using mechanical methods" also a widely accepted methodology for the fabrication of nanomaterials [8].
1)Top-Down (Large-Downward) Methodo-logy:
The reduction in size of the components required for the fabrication of necessary electronic devices and machines is currently engaged by the top-down (large- downward) methodology. This methodology, which guides engineers and other professionals like physicist etc. to control and organize increasingly smaller particles of matter by photolithography and other related techniques has been utilized in a good way. It is becoming more and more evident, however, that current computer technology that depends on silicon-based chips is continually approaching the limits of its physical capabilities [9], and likewise photolithography is affected to drastic limitations for dimensions that are smaller than 100 nanometers. By the general standards of our day to day experience these are relatively very smaller sizes (about one thousandth the size of our hair), but when compared these in atomic and molecular scales these are very large (tenth of nanometers).
Henceforth, "there is plenty of room at the bottom" for further reduction, as Richard P. Feynman [9] stated when he addressed to the American Physical Society in 1959. In 1965 G.E. Moore stated that every three years (1) the size of the devices would reduce by 33%, (2) the size of the chips used in electrical devices will increase by 50%, and (3) the number of components integrated in a chip would be fourfold [10]. Such anticipation has been accomplished until now and the capability of laser laser techniques in our large-downward approach to reduce the size of the components is being worked upon for fabrication of microelectromechanical systems (MEMS). A suitable example for the defining the top-down approach is shown by the fine features of the bull shown in Fig.1. The figure of the bull is crafted by two- photon photopolymerization [9].
Fig.1. Scanning electron micrographs of bull sculptures crafted on a resin by two-photon photopolymerization, showing the definition reached by top-down miniaturization. These sculptures are 10micrometer long and 7 micrometer high, and are about the size of a red blood cell [9].
2)Bottom-Up(Small-Upward) Methodology:
The Bottom-Up methodology offers an alternate and promising strategy towards technology at nanoscales that ranges from atomic or molecular levels and extends up to nanostructures. Professionals in the field of chemistry would be in an apt position to develop the bottom-up methodologies for the fabrication of nanoscale devices and their equipments.
The bottom-up (small-upward) methodology in molecular electronics is relatively fresh. Recently only nanoelectronics were atleast even considered as an attainable objective by the physicists [9]. The idea of nanoelectronics was recently (few decades) derived from quantum theory and it was that the atoms are fuzzy entities that "must no longer be regarded as identifiable individuals" [11], and " form a world of potentialities or possibilities rather than one of things or facts" [12]. If we consider the quantum theory, then from that point of view molecular structure is a metaphor rather than an inherent attribute [9]. The whole concept of this bottom-up methodology has been presented well by a great chemist and writer, Primo Levi, in his book "La Chiave a Stella" [9].
The ability to manipulate the coordination and structure of a matter in the scale of 1-100nm length is thus an essential study topic for researchers in areas ranging from electronics, to physicist, to medical engineering in nanoscale systems. Here comes the significance of nanolithography which deals with study and application of constructing nanoscale components for electronic and other nanodevices.
NANO LITHOGRAPHY:
Nanolithography is the present day scenario for the fabrication of state of the art semiconductor integrated circuits. It widely implies in the field of nanoelectromechanical systems and nano ciruits. It has become an active area of research related to electronic industries and studies.
1)Nanoimprint Lithography (NIL):
Nanoimprint lithography (NIL) is a recently emerged revolutionary fabrication technology which demonstrates sub 10nm resolution and high efficiency at considerably low expenditure[14-17]. NIL has been valued as one of the most anticipated methodology for the fabrication of nanoscale devices. It is looked upon as the satisfying future fabrication demands of the semiconductor industry. The advancements in this field is only possible if the achievements of NIL methodology is used to enhance the performance and throughput of existing NIL strategies also at the same time exploit new unconventional ways to employ its processes for manufacturing new nanoscale materials and components[18, 19]. The NIL technique can be further sub categorized based on the medium and environment mainly used while fabrication of devices.
Molecular-Beam-Epitaxy (MBE) at Room Temperature:
It is a type of NIL technique in which at room temperatue molds are fabricated by Molecular-Beam-Epitaxy (MBE) and in turn these molds are imprinted. In his way the thickness of developed crystalline layers with nanometer resolution can be accurately controlled. The nanoscale resolution directly ascertains the minimum size of the mold features that are to be imprinted [18].
Imprint Mold Fabrication by Using MBE:
Imprint mold fabrication methodology basically constitutes of three process steps: (1) first step is to grow a layer of crystalline material Y above the substrate material X. The materials X and Y must be chosen in such a way so that they can be etched selectively with respect to each other., (2) second step is to grow a layer a second layer of material X over the crystalline layer of material Y. (3) finally in the third step the three layers are etched in such a way that the whole structure is perpendicular to the direction in which the layers are grown.
Also it should be kept in mind that the grown layers should be properly wet-etched at all edges. The structure obtained after performing the wet-etching process constitutes a three dimensional topographical surface structure forming either a positive line feature (material X etched quicker with respect to Y) or a negative groove setup (material Y etched quicker with respect to X). When More than two different materials are grown on top of the substrate and selectively wet-etched it produces a quasi-arbitrary three dimensional grating. Monolayer precision is employed to control the thickness of MBE-grown layers with nanometer resolution.
Fig.2. Single line MBE-mold (SEM): SEM top-view image and AFM cross section image of the 3D surface profile of a MBE-mold after selective etching. The white area on the far right side of the image is the surface area of the grown GaAs layer [20].
Fig.2. gives an example of a Single-line MBE-mold which uses GaAs as substrate material and the second crystalline material used is a compound AlGaAs. The thickness of the AlGaAs layer shown in Fig.2. is 300nm and finally during the last step 300nm wide and 400nm deep groove where AlGaAs was etched away. Hence a negative groove is formed and this inturn is used to imprint a positive line of same width into a layer of polymer [20].
Furthermore the MBE-molds can be classified into two: (1) Single-line molds and (2) multi-line molds. But the substrate material used for both kinds of molds will be of the same GaAs material.
Fig.3. Two types of multi-line MBE-molds [20].
UV-Nanoimprint Lithography (UV-NIL):
A wide range of NIL methodologies utilizes UV rays to heal already formed polymers before the mold release establishes the key prospects of this technique of fabrication for attaining high throughput pattern of large areas at nanolevels. Advancement in this field of UV-NIL is the development of a strategy which has been designated as combined Thermal and UV- nanoimprint lithography (TUV-NIL) [21, 22].
Combined Thermal and UV- Nanoimprint Lithography (TUV-NIL):
The process of TUV-NIL employs the advanced epoxy-based polymer for imprinting mr-NIL 6000 which is custom-developed for the TUV-NIL processes. The mr-NIL 6000 polymers are used to attain certain properties like good thermal stability and also release properties. The main advantages of TUV-NIL over conventional thermal NIL and conventional UV-NIL are: (1) the TUV-NIL operations are carried out at the same temperature hence no cooling of polymer is required. (2) In TUV-NIL the embossment polymer is spun onto the substrate material and hence more accurate control over thickness of the polymer [21, 22]. Hence the time to complete one cycle of TUV-NIL fabrication process is much shorter than the conventional methods.
Fig.4. SEM top-view images of square patterns with 200nm feature sizes: (a) imprinted mr-NIL 6000 surface after completing a TUV-NIL process, and (b) silicon oxide surface as a result of the pattern transfer process of the pattern shown in (a) using reactive ion etching (RIE) in an oxygen plasma followed by a fluorine based RIE step [21, 22].
The demands and issues concerned with nanoimprint lithography is addressed and discoursed in the above sections of the paper. Thus nanolithography is considered as a fresh fabrication technology for the construction of components that are essential for the building of nanoscale materials and devices with high efficiency and low expenditure.
APPLICATIONS:
The basis of any nanoelectronic circuitry is contained in the devices employed to build it. As in case of traditional very large scale integration (VLSI) systems: copper wire and silicon transistors. Similar is the case for nanoelectronics. The ordinary copper wires and transistors are but replaced by carbon nanotubes (CNTs) and silicon nanowires (SNWs) generally because of their chemical properties and due to which they can be manipulated at smaller sizes. Number of applications exists that could easily replace transistor as their basic logical device, such as: nanowire, reconfigurable switches, quantum cellular automata etc.
1) Silicon Nanowires:
Semiconducting nanowires (NWs) are employed as interconnecting wires for carrying signals along with an active device. Unlike a CNT a single NW can act as both as an active device and an interconnect wire. NWs are long thin wires built up of different semiconducting materials generally silicon or germanium and which in turn has a thickness of 3nm and length of upto 100μm [23-25].
Fabrication:
The fabrication of NWs involves processes such as LASER ablation, VLS synthesis and chemical vapor deposition or by combining a couple of these methods, the same methods as that are involved in the fabrication of CNTs with a minor exception of the use of carbon instead of silicon. When NW is used instead of semiconductor, the control of dopant levels of the NWs should be along with its length and this whole process is dependent on its method of growth.
Generally materials such as boron or phosphorus are added to the vapor to fabricate semiconducting NW. One of the techniques used for fabrication is vapor-liquid-solid (VLS) technique as shown in Fig.5. By which crystal layers are grown with the aid of a liquid catalyst or solid like gold. Then the liquid catalyst is placed with the vaporized semiconductor material in a heated chamber of high temperature. The catalyst absorbs the semiconductor material until becomes supersaturated and begins to form a crystalline solid at that point and the process continues until the semiconductor material is used up or until the liquid catalyst solidifies [24, 25].
Another method employed for the fabrication of NWs is laser ablation technique from which we can obtain catalysts with uniform diameter which then subsequently aids in the process of fabrication of uniform thickness NWs with relatively uniform electrical characteristics.
Fig.5. A suggested silicon nanowire growth method by laser ablation method with iron and silicon as catalyst and semiconducting materials respectively [24].
The contained growth of the fabricated NWs allows the doping along the length of the NWs to be varied. For NWs with a core made up of semiconductor and also with an insulated covering, during the final steps of fabrication the NWs are coated with different materials. These coatings are obtained as result of vaporizing another fabricated NW with a new material which in turn leads to the formation of a thin uniform sheath [27]. The NWs can be really heavily doped that the NWs begin to conduct as an p-type or n-type conductor.
Nanowire Electrical Devices:
Active devices can be integrated into a NW by proper control of the doping agents along the length of the wires. For example a field effect transistor can be attained from a NW with small sections containing fewer amounts of carriers than the rest of the wire. Active devices such as a p-n junction diode can also be implemented using a single NW which can be achieved by growing a part of the NW with a p-type dopant subsequently switching to an n-type dopant during the fabrication of remaining NW [26].
One of the appealing advantage of NWs over other conventional electronic devices is their ability to grow hundreds of micrometers in length which substantially justifies the use of NWs as both as an interconnect wire as well as device. The CNTs demonstrates ballistic conduction whereas NWs conduction is regulated by its edge effects, also due to its size it displays unique electrical properties. Nevertheless, NWs are not completely bonded as they are basically a solid wire. While the core of the NW is metallic so it conducts and the atoms on the exterior of the wire reduce the conductivity of wire because of the defects in the crystal structure. The shrinking of the NWs results in representation of atoms on the surface of the wire progressively of the overall structure. Hence brings upon decline in the overall conduction of the NW. This property of NWs is considered as one of the serious demerits of NWS [22].
CONCLUSION
Nanoelectronics is indeed a disruptive technology that can be visualized as the future of electronics, as it is being employed in many fields these days to acquire better performance from the conventional methods such as to cut down the cost of fabrication of devices and to achieve highly considerable computational efficiencies. Nevertheless as discussed above in the paper, yet there are some challenges and issues that is to be dealt with.
