High Performance TAM Controller And Wrapper Design For Embedded Cores
Abstract
IEEE 1500 is a standard under development which intends to amend ease of test reuse and test integration with respect to the core-based system-on-chip(SoC). The subject paper proposes evolving the wrapper cell design for SoC testing used in the IEEE 1500 standard for digital embedded cores. The digital cores used in the study were constructed from ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits. The wrapper that separates the core under test from other cores is assumed to be IEEE 1500- compliant. The test access mechanism plays an important role in transporting the test patterns to the desired core and the core responses to the output pin of the SoC. The faults were injected using a fault simulator that generates tests for the core. The cores and test access mechanism were described using VHDL. The test access mechanism (TAM) provides the connection between the test sources, cores, and test sinks, which is crucial in any SoC design. The outcome was the fault coverage of all the cores being tested. Area overhead and power consumption are taken into account in our scheme. Experiment results based on a sample SoC are reported, showing the effectiveness of the proposed approach in terms of area overhead and power consumption.
Introduction
Large-scale integration has added enormous complexity to the process of testing modern digital circuits. Besides, during the past several years, integrated circuit technology evolved from chip-set philosophy to embedded cores based system-on-a-chip (SoC) concept [1], which simply refers to an IC, designed by stitching together multiple stand-alone VLSI designs to provide full functionality for an application. Though many aspects of these embedded cores-based systems and SoC are still evolving, they are revolutionizing the electronics industry. These innovations are already on their way to the next generation of cell phones, multimedia devices, and PC graphics chipsets. The cores-based design, justified by the necessity to decrease time-to-market, has created a host of challenges for the design and test community [4][9]. The core test integration is a complex problem - the chip integrator can modify the test and add design for test (DFT) and built-in self-test (BIST) features, if necessary. Specifically, in the context of embedded cores-based system testing, electrical isolation involving the input and output ports of the core from the chip or other cores is a necessity. The fundamental items of interest in core test is access, control, and isolation, and these are the issues which were addressed by the IEEE Technical Council on Test Technology Working Group 1500[2] entrusted with the responsibility of developing standard architecture for their solution. The embedded core test requires, in general, hardware components like wrapper around the core, a source and a sink for test patterns (on-chip or off- chip) and an on-chip test access mechanism (TAM) to connect the wrapper to the source or sink. The cores could be without boundary scan or with boundary scan. For design and test reuse, ASIC manufacture has suggested certain characteristics. In general, different DFT and BIST schemes like scan, partial scan, logic BIST and scan-based BIST are used to test various logic blocks within a SoC like microprocessor or microcontroller. However, the main problem is still the resulting area overhead and performance penalties. Structural test methods like scan and BIST are desirable for test reuse, portability, and test integration into the SoC test set. The TAM includes on-chip test generation logic for cores with BIST. The DFT techniques involve adding optimized test logic within cores and at the chip level to enhance testability and DFT logic helps test pattern generation and application, and assist in the support test environment. In this paper, test methodologies are proposed for embedded cores-based system-on-a-chip (SoC) digital systems comprising of wrapper and TAM. The fault model used is the conventional single stuck-fault model. The nature of faults is single stuck faults. Thus each line can have only two types of stuck faults: stuck-at-1 and stuck-at-0. The IEEE 1500-compliant [2] wrapper separates the core under test from other cores. The TAM plays a vital role in transporting the test patterns to the desired core and the core responses to the output pin of the SoC. The TAM was implemented as a plain signal transport medium, which is shared by all the cores in the SoC. Once the compilation of the cores was done, the fault simulation was carried out with the test patterns feeding the cores through the TAM. The selection of the appropriate core is taken care of by the program running in the background. The simulation process is completely automatic, and requires no intervention from the designer during the test generation process. This paper describes the architecture of the wrapper and test access mechanism, together with models of the SoCs being used, based on application environment.
1500-Based Soc Test Integration Architecture
The IEEE 1500 wrapper has various modes of operation. There are modes for functional (nontest) operation, inward facing (IF) test operation, and outward facing (OF) test operation. Different test modes also determine whether the serial test data mechanism (WSI-WSO) or the parallel test data mechanism (WPI-WPO), if present, is being utilized. Instructions loaded into the Wrapper Instruction Register(WIR), together with the IEEE 1500 wrapper signals, determine the mode of operation of the wrapper and possibly the core itself. There is a minimum set of instructions and corresponding operations that shall be supplied. Optional instructions and their corresponding behavior are also defined, together with the requirements for extension of the instruction set. All instructions that establish test modes that utilize the parallel port WPI and WPO are optional, as the presence of this port is optional. Furthermore, IEEE 1500 also allows for user-defined instructions.
IEEE 1500[2] has a set of instructions that are defined to use only the serial interface (WSP) and a corresponding set of instructions that are defined for the parallel interface. IEEE 1500 must allow accessibility to test the core. There is one main core test instruction—Wx_INTEST (user-specified core-test instruction)—that is flexible enough to allow any core test to execute. There are two other instructions that are mandatory: an instruction for functional mode (WS_BYPASS) and an instruction for external test mode (WS_EXTEST). WS_BYPASS puts the wrapper into the bypass configuration and allows access to all functional terminals of the core shown in Fig 1. WS_EXTEST is the serial EXTEST configuration of the wrapper. Even if there is a WP_EXTEST mode (for parallel access), there must still be a WS_EXTEST instruction capability. The signal connected to the WRCK terminal is a dedicated clock used to operate IEEE 1500 functions.
Components
Test Access Mechanism (Tam) And Wrapper
The design of test access mechanism (TAM)[4] and test wrapper is of critical importance in terms of system integration since they directly impact hardware overhead, test time, and tester data volume. The main issues in this context are wrapper optimization, core assignment to TAM wires, sizing of TAM, and TAM wire routing.
There are two important concepts related to TAM, viz. test pattern source and sink, and core wrapper. The test pattern source is responsible for generating the test vectors or test stimuli for the desired core under test. The test pattern sink compares the fault-free response to the faulty response of the core under test. The test pattern source and sink can be built on-chip or off-chip. In our case, we implemented this by using the fault simulator that generates the test vectors, and after getting the test response, compares it with the fault-free response. We will briefly discuss about fault simulation later. There are several ways to design and implement a TAM . The common TAM architectures are: 1) daisy chained TAMs (that use serial shifting of test data); 2) bussed TAMs (based on use of complex protocols); direct access TAMs (for cores with many inputs and outputs); and 4) multiplexer (MUX)-based direct access TAMs. In this paper, MUX-based direct access TAM architecture, as shown in Fig. 2 is implemented. The TAM is used to drive the test vectors from the test source, that is, from the fault simulator to the desired core under test and to transport the test response from the core back to the fault simulator. The selection of the core in the SoC was implemented as part of the TAM architecture. The width of the TAM by the core that has the maximum number of input/output (I/O) pins within the SoC is determined. There are other issues for consideration at this phase, viz. the bandwidth of the TAM versus the cost of extra wires needed for its implementation, total test time depending on the TAM bandwidth, test vectors from the source, and ultimately test data for the individual core. The obvious mechanism to make embedded cores testable from the IC pins [10] is to make the core under test directly accessible from the IC inputs. Though this approach is mostly practiced for embedded memory cores, many block-based ASICs also use this test strategy.
Tam Controller Design
As shown in Fig. 3, TAM controller is used to provide the dynamic control signals to wrapper , i.e., WIP. WIP is composed of six signals: WRCK, WRSTN, SelectWIR, ShiftWR, CaptureWR and UpdateWR. At the exception of WRSTN, all WIP signals are active high. The following are the different signals used.
TAM controller can be used, as long as its outputs fully conform to the requirement of WIP. TAM controller is a Finite State Machine (FSM) in nature. Since WIP signals mimic the output of Test Access Port (TAP) controller of IEEE 1149.1[9], here the same state-diagram as TAP (Fig. 3) is used and the output logic of FSM is modified in order to make it suitable for WIP. The three inputs (tclk, tms, trst) of TAM controller have just the same meaning as in TAP, that is, TAM controller changes its state on the rising edge of tclk according to tms. In our design, tclk is also used as WRCK.
Wrapper Design
P1500 wrapper consists of WIR, wrapper bypass register (WBY), wrapper boundary register (WBR), gating control logic, mandatory serial path, and optional parallel paths. The serial path is used both for wrapper control by loading instructions into WIR, as well as for low-bandwidth test data access to WBR. Parallel paths are used for internal scan-chains and high-bandwidth test data access to WBR. A minimal library of WBR cells is presented and the design of WBR is not depicted in this paper. WBY used in our wrapper is just an ordinary flip-flop. Bypass registers both for the serial path and parallel paths are inserted.
WIR is composed of shift register, update register and decoding logic . At the start of every test cycle, a new instruction is shifted into WIR through the serial path. Consequently, the operation of the wrapper is controlled by both WIP signals, as well as the presently active instruction in WIR. WIR outputs two static control signals for the wrapper. Sel identifies whether WBR or WBY is connected between WSI and WSO and M2_Mode determines whether the test data in WBR apply to system logic or not. WRSTN resets the content in the update register and puts the wrapper in normal operation mode.
Core Test Generation And Test Environment
The cores we used for our purpose were constructed from ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits. The problems related to testing sequential circuits are much more complicated than those for the combinational circuits. The basic reason is the presence of storage elements in the realization of sequential circuits. The testing time is also generally higher in the case of sequential circuits. The test generation was focused at the gate level based on single stuck-fault model. The first step in our SoC test generation procedure is to obtain specified sets of test vectors using high-level descriptions of circuit cores. We endeavored to improve upon the process by using automatic test generation for high fault coverage.
All the SoCs used in the paper were designed to operate in Altera Max Plus II development environment. The SoC cores and the TAM are designed to work, described in VHDL. The process of fault injection for the different SoC cores was carried out by the designed fault simulator. It first injects faults at the input lines, then at the output lines, which were followed by fault injection at the internal wires. The nature of faults is single stuck faults. A line with a stuck-at-1 fault will always have a logical value 1 irrespective of the correct logical output of the gate driving it. Simulation based fault injection scheme is used to evaluate the dependability of the system based on the percentage of fault coverage. Each line is injected either with a stuck-at- 1 or with a stuck-at-0 fault. The fault simulator makes a fault list of all stuck-faults on the inputs and outputs of gates and functional blocks. The simulator then simulates the circuit core with the selected faults by using the given test vectors. It keeps a record of the detection data (time and output of detection) for each fault and also stores the true-value response. Each vector set is run through the simulator by using the list of undetected faults up to that point. At the end of a run, the simulator can store the internal states of the circuit core in a checkpoint data set for use by the next vector set. This data set is provided to the test program and the fault coverage is finally calculated.
Implementation Results
To demonstrate the feasibility of the developed test environment and test methodologies for embedded cores based SoCs, independent simulations were conducted on the SoCs that is constructed based on ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits. We first provide here simulation test data on a SoC that was constructed from the sequential circuits in ISCAS 89 benchmark circuits list. Next, simulation experience on a SoC comprised of the combinational circuits in ISCAS 85 benchmark circuits list is given. Finally, we consider SoCs comprised of both sequential and combinational circuits from ISCAS 89 and ISCAS 85 benchmark circuits lists, respectively.
Power Consumption Result
The power consumptions of both ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits on a Xilinx Virtex II FPGA are estimated using Xilinx XPower tool. In order to estimate the power consumption of a core, timing simulation of the placed and routed netlist of that core is done using ModelSim SE and the signal activities are stored in a VCD file. This VCD file is used for estimating the power consumption of those circuits with wrapper implementation using Xilinx XPower tool. In addition, we applied clock gating and glitch reduction techniques to core data path for reducing its power consumption as shown in table.
Conclusion
Embedded cores-based design prototype has developed from the necessity to increase design productivity and decrease time-to-market, but as a result has created numerous challenging issue for the test design community. Keeping in view the many formidable issues that arise in testing these cores-based SoCs, the present paper provides approaches to developing test environment and test methodologies for digital SoCs. A 1500-compliant wrapper and TAM controller co-design scheme is presented in this paper. In this scheme, only one TAM controller is required at SoC level hence costing low area overhead. The test access mechanism which plays an important role in transporting the test patterns to the desired cores and the resulting responses to the output pins of the SoC was implemented as a plain signal transport medium, being shared by all the cores in a given SoC. The faults were injected using fault simulator that generates tests for the core under test. The selection of the individual cores was taken care of by the program running in the background. Testing power consumption of the wrapper is also taken into account by using gated clocks to operate wrapper registers. The effectiveness of the proposed scheme has been confirmed by experiment results based on a sample SoC.
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