IEEE STD 1500, standard for Embedded Core Test, is a standard with respect to various aspects of core-based testing. The IEEE std 1500 targets easy integration and interoperability for testing strategies addressing many manufacturing defect types, especially when various cores of different sources are brought together in one system chip. System chips are increasingly designed by embedding reusable cores. A core-based test strategy for such ICs is often attractive and sometimes even mandatory. IEEE P1500 SECT is a standard under development that standardizes a Core Test Language and a Core Wrapper, in order to facilitate plug-n-play core testing. Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e. the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. The test application time must be minimized, and a test access mechanism must be developed to transport test data to and from the cores. The cost of testing SoCs (System-on-Chip) is highly related to the test application time. The problem is that the test application time increases as the technology makes it possible to design highly complex chips. The subject paper proposes developing TAM/wrapper design for embedded cores based system-on-a-chip (SOC). The wrapper that classifies the core under test from other cores is assumed to be IEEE P1500- compliant. The test access mechanism plays an important role in carrying the test patterns to the desired core and the core responses to the output pin of the SOC. Experimental results on savings in test application time and the low hardware overheads for a benchmark SOC demonstrate the effectiveness of this approach.
Keywords - Built-in self-testing (BIST), embedded cores-based system-on-a-chip (SoC), sequential circuits, test access mechanism (TAM), test pattern generator (TPG), VHDL, wrapper.
INTRODUCTION
Large-scale integration has added tremendous complexity to the process of testing modern embedded circuits. Besides, during the past several years, integrated circuit technology developed from chip-set philosophy to embedded cores based system-on-a-chip (SoC) concept, which is refers to an IC, designed by running up together multiple stand-alone VLSI designs to provide full functionality for an application. Though many aspects of these embedded cores-based systems and SoC are still evolving, they are revolutionizing the electronics industry. These innovations are already on their way to the next generation of cell phones, multimedia devices, and PC graphics chipsets. The core-based design, ensured by the requirement to decrease time-to-market, has created a host of challenges for the design and test standard. Unlike conventional test design approaches, SoC makes it impossible to establish the contrast lines between design and test. For mixed-signal devices and complex digital cores, engineers must use design tools that let them incorporate testability early in the design process. The core test integration is a complex problem - the chip integrator can modify the test and add some design for test (DFT) and built-in self-test (BIST) features, if necessary. Specifically, in the context of embedded cores-based system testing, electrical isolation involving the input and output ports of the core from the chip or other cores is a necessity. The fundamental items of interest in core test is access, control, and isolation, and these are the issues which were addressed by the IEEE Technical Council on Test Technology Working Group 1500 entrusted with the responsibility of developing standard architecture for their solution. The embedded core test requires, in general, hardware components like wrapper around the core, a source and a sink for test patterns (on-chip or off chip) and an on-chip test access mechanism (TAM) to connect the wrapper to the source or sink. The cores could be without boundary scan or with boundary scan. For design and test reuse, ASIC manufactures have suggested certain characteristics. In this paper, test methodologies are proposed for embedded cores-based system-on-a-chip (SoC) digital systems comprising of wrapper and test access mechanism (TAM). The cores considered in the study were constructed from ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits. The fault model used is the conventional single stuck-fault model. The wrapper separates the core under test from other cores, which is assumed to be IEEE 1500-compliant. The test access mechanism plays a vital role in transporting the test patterns to the desired core and the core responses to the output pin of the SoC. The faults were injected using a fault simulator that also generates the test sets for the cores. The test access mechanism (TAM) was implemented as a plain signal transport medium, which is shared by all the cores in the SoC. Once the compilation of the cores was done, the fault simulation was carried out with the test patterns feeding the cores through the TAM. The selection of the appropriate core is taken care of by the program running in the background. The automatic fault simulator generates tests for the core described at the gate and flip-flop level. There are very few constraints on the core being tested. The simulation process is completely automatic, and requires no intervention from the designer during the test generation process. The subject paper describes the architectures of the wrapper and test access mechanism, applications of the fault simulator, together with models of the SoCs being used, based on application environment. Some partial simulation results using the designed cores are also provided to demonstrate the feasibility of the proposed implementations.
IEEE 1500 scalable hardware architecture
IEEE Std 1500 distinguishes the heterogeneous perspective of the embedded core market, i.e., a variety driven by the necessitate to cover a variety of design functions implemented in digital logic, analog logic, memory, radio frequency (RF), field-programmable gate arrays (FPGAs), or combinations of the above. Cores come in many different "flavors" (e.g., hard, firm, soft) and are being used and/or sold within companies as well as between companies. Within its focus on nonmerged digital logic and memory cores, IEEE Std 1500 intends to support the above diversity and associated business models. Different test modes also determine whether the serial test data mechanism (WSI-WSO) or the parallel test data mechanism (WPI-WPO), if present, is being utilized.
The IEEE 1500 core wrapper comprises the following:
Serial interface terminals forming the WSP
A user-defined set of wrapper terminals forming the wrapper parallel port (WPP) and providing parallel access to the wrapper
A WIR
A WBY
A WBR
Figure 1-Standard IEEE 1500 wrapper components
Wrapper serial port (WSP)
The WSP terminals serve as the primary interface to the IEEE 1500 wrapper. This set of serial terminals could be sourced from chip-level pins or from an embedded controller such as an IEEE 1149.1-based controller. The WSP is used to load and unload instructions and data into and out of the IEEE 1500 registers. In addition to the wrapper serial input (WSI) and wrapper serial output (WSO) terminals shown in Figure 1, the WSP contains wrapper serial control (WSC) terminals used to control the operation of all IEEE 1500 registers.
The WSP includes the following mandatory terminals: WSI, WSO, and a set of WSC terminals. The WSC comprises the wrapper clock (WRCK), wrapper reset (WRSTN), SelectWIR, CaptureWR, ShiftWR, and UpdateWR terminals. If required for operation of the WBR, the optional TransferDR terminal is also included in the WSC.
Fig2 :Wrapper serial port
Wrapper instruction registers (WIR)
The WIR enables all IEEE 1500 wrapper operations. This register is loaded via the WSP with instructions that select an IEEE 1500 data register. The WIR can optionally be interfaced to the core for establishing test mode or functional operation. The WIR is an instruction register in which IEEE 1500 wrapper instructions are serially loaded through the standard WSP. The WIR also comprises interface circuitry to other IEEE 1500 components, such as the WBR and WBY, and may also interface to the circuitry of the core
Fig 3: Wrapper instruction registers
Wrapper bypass register (WBY)
The WBY provides a bypass path for the WSI-WSO terminals of the WSP. The WBY is the default data register between WSI and WSO and should be selected by the current wrapper instruction when no other data register is selected. The WBY is intended to provide a minimum length scan path through the wrapper, so that when several IEEE 1500 wrappers are serially chained together in a system on chip (SoC), the wrappers that do not require a data register to be accessed can be bypassed with a short scan path through their WSIWSO terminals.
Fig 4: Wrapper bypass register
Wrapper boundary registers (WBR)
The WBR is the data register through which test data stimuli are applied and pattern responses are captured. This register allows internal testing of the core, as well as testing of external connectivity to other cores and SoC integration circuitry, in response to an instruction loaded into the WIR.
TAM CONTROLLER DESIGN
The TAM is used to provide the core-based SOC with an architecture for transporting test stimuli from the tester to the wrapped cores and transporting produced responses from the wrapped cores to the tester.
In Direct access, the number of TAM wires, WTAM, is equal to the total number of core terminals in the SOC, therefore, direct access requires a large wiring overhead when the total number of core terminals is large. The Multiplexing architecture contains only one TAM that connects all cores in the SOC and only one core can be accessed at a time, hence, the cores are tested sequentially. The overall test application time of the system is, therefore, the sum of all the individual core's test application times. The Daisychain architecture also uses one TAM to connect all cores, however, in contrast to the Multiplexing architecture, the Daisychain architecture allows multiple cores to be accessed at a time. The wrapper chains of all cores are connected into long chains, from the inputs, through all cores, to the outputs. In the Distributed architecture each core has its own dedicated TAM, and all cores are tested in parallel. The sum of each TAM's width is the full TAM width of the system. The overall test application time for the system is given by the core with the longest test application time.
Fig 5: TAM CONTROLLER
CORE TEST GENERATION AND TEST ENVIRONMENT
The cores we used for our purpose were built from ISCAS 89 benchmark circuits. The problems related to testing sequential circuits are much more complicated than those for the combinational circuits. The basic reason is the presence of storage elements in the realization of sequential circuits. The testing time is also generally higher in the case of sequential circuits. The test generation was focused at the gate level based on single stuck-fault model. The first step in our SoC test generation procedure is to obtain specified sets of test vectors using high-level descriptions of circuit cores. We endeavored to improve upon the process by using automatic test generation for high fault coverage.
All the SoCs used in the paper were designed to operate in Altera Max Plus II development environment. Not only was the SoC cores, the test access mechanism (TAM) also designed to work described in VHDL. The process of fault injection for the different SoC cores was carried out by the designed fault simulator.
IMPLEMENTATION RESULT
To establish the feasibility of our formulated test environment and test methodologies for embedded cores- based SoCs, independent simulations were conducted on the cores of the various SoCs that we built based on ISCAS 89 benchmark circuits. The simulation data on an SoC that was constructed from the sequential circuits in ISCAS 89 benchmark circuits list.
Fig. 4 shows the number of injected faults, detected faults, and fault coverage for the first SoC (SoC_seq) using pseudorandom test vectors. Fig. 5 shows the result for core area with wrapper for our experimental SoC.
Circuit name
No. of Test vectors for Simulation
No. of fault
injected
No of faults detected
Fault Coverage (%)
S27
32
9
7
77.77
S298
16
4
4
100
C17
20
6
5
83.33
Fig. 6: Test Data for the cores
Core
Slices
Core Area With Wrapper
C27
2
109
S27
4
114
S298
16
127
Fig.7: Core Area with Wrapper
CONCLUSIONS
System chips are increasingly designed using embedded reusable cores. For such core-based SOC designs, a core based test strategy is attractive because of the reuse of the core's test patterns. For cores of which the implementation contents is blotted out from the system chip integrator, it is even required to reuse the tests as delivered by the core provider.SOC cores-based design paradigm has evolved from the necessity to increase design productivity and decrease time-to-market, but as a result has created numerous challenging problems for the test design community. A 1500-compliant wrapper and TAM controller co-design scheme is presented in this paper. In our scheme, only one TAM controller is required at SoC level hence costing low area overhead. The test access mechanism which plays an important role in transporting the test patterns to the desired cores and the resulting responses to the output pins of the SoCs was implemented as a plain signal transport medium, being shared by all the cores in a given SoC. The faults were injected using fault simulator that generates tests for the core under test. The selection of the individual cores was taken care of by the program running in the background. Testing power consumption of the wrapper is also taken into account by using gated clocks to operate wrapper registers. The effectiveness of the proposed scheme has been confirmed by experiment results based on a sample SoC.
