1. Introduction
It has become apparent that the severe underutilization of the electromagnetic spectrum [7] calls for alternative and novel solutions in the utilization of the radio resource. The process of statistically gathering and interpreting data to provide spectrum management information is called Spectrum Sensing. These types of activities require high processing power and reconfigurable hardware platforms. An optimum solution is Software Defined Radio (SDR) Platforms.
1.1. Spectrum Sensing
A standard for a Cognitive Wireless Regional Area Network (WRAN) is being developed by the 802.22 working group, which will exploit unused DTT channels and provide fixed wireless access services. It is expected that the final standard will support 6, 7 and 8 MHz channels. The standard's draft form can be found in [8].
Sensing involves the analysis of the radio frequency spectrum and identifying unused spectrum for use by the WRAN [3].
The type of sensing used by the authors in this paper is called Energy Detector, a blind sensing technique that does not rely on any special signal features detection (i.e. correlation).
1.2. Energy DetectorSensing
The energy (power) detector is a type of sensing that estimates the signal power in the channel and compares that estimate to a threshold [4].
One aspect of this process is to perform non-coherent detection through energy detection. An energy detector can be implemented analogous to a spectrum analyzer by averaging frequency bins of a Fast Fourier Transform (FFT).
There are several drawbacks of energy detectors that can diminish their simplicity in implementation like: the threshold used for primary user detection is highly susceptible to unknown or changing noise levels; energy detection does not differentiate between modulated signals, noise and interference and, therefore, cannot benefit from adaptive signal processing for canceling the interferer; an energy detector does not work for spread spectrum signals like direct sequence and frequency hopping signals, for which more sophisticated signal processing algorithms need be devised [2].
1.3. Software-Defined Radio
The novelty of the sensing system, described in this paper, is its reliance upon a SDR system.
A SDR system is made up of a SDR hardware platform and its associated software framework and functionality.
The term Software Defined Radio was coined in [1] by J. Mitola, and described as being the process of building digital communications systems by employing general purpose hardware and pairs of digital to analog (DAC) and analog to digital converters (DAC and ADC) for digital signal processing.
GNU Radio founder Eric Blossom, states in [12] that SDR is the technique of getting code as close to the antenna as possible. The concept is to turn radio hardware problems into software problems which are more flexible and manageable. SDRs generate, modulate / demodulate the transmitted /received waveforms, contrary to most radios, which do their processing through analog or combined analog and digital circuitry.
To sum up, a SDR or frequency-agile radio, module is capable of reconfiguring and switching to newly-selected frequency bands. It can be programmed to tune to and operate on specific frequency bands over a wide range of spectrum [6].
2. Sensing System Architecture
A typical SDR based Cognitive Radio Sensing System architecture and its functional blocks are depicted in Figure.1.
The SDR Hardware Platform is usually comprised of the Radio Frequency Front-End and the SDR MotherBoard Blocks.
The RF Front-End collects the signal from the antennae, after which it filters, amplifies and tunes the signal to a baseband frequency dependent on the board's IF bandwidth and local oscillator frequency.
The signal is then passed to the SDR Motherboard block. Here, an analog to digital converter (ADC) samples the received signal and converts it to digital values depending on the ADCs dynamic range. The digital sample values are transferred to the FPGA and processed with digital down converters (DDC) to meet exactly the requested output frequency and sample rate [13]. This is done by multiplying the samples with a sine, respectively cosine, function resulting in the I and Q paths. The frequency is generated with a numerically-controlled oscillator (NCO) which synthesizes a discrete-time, discrete-amplitude waveform within the FPGA. The next step is signal decimation by an arbitrary decimation factor, N. The resulting signal is the SDR platform's output signal towards the host side [13].
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While able to perform basic digital signal processing (DSP), with its General Purpose Processors and FPGAs, the SDR platform's limited processing capabilities require the processing power of the Host Computer Block. This is usually a personal computer (PC) with sufficient processing power, able to run the appropriate software. The System Software Block is a collection of explicit DSP software, capable of implementing sensing-specific statistical algorithms and functional flows. This block is run by the Host Computer.
2.1. Software Defined Radio Platform
SDR hardware platforms were studied as to determine the optimum candidate concerning the required, functionality to cost, ratio. The first term, functionality, indicates that the proposed system clearly satisfies its purpose, namely agile spectrum sensing in order to identify unused radio channels. The second term of the ratio, cost, implies that, as long as the functionality of the system is satisfactory, it should remain to a minimal value.
Table 1 portrays the differential analysis for available RF front end solutions.
According to the “functionality to cost” paradigm, proposed by the authors, it clearly emerges from table that the optimum solution is Ettus Research's platform, entitled Universal Serial Radio Peripheral 2 or USRP2.
In USRP2s, ADCs have a dynamic range of 14 bits and a sampling rate of 100 mega samples per second (MS/s).
Towards the host side, USRP2 uses the Gbit-Ethernet connection, allowing a significantly high throughput. The theoretical data rate of 125 MB/s allows for a theoretical (complex) RF bandwidth of about 31.25 MHz, although the usable bandwidth has a limit of 25 MHz.
USRP2 daughterboards are RF front ends that plug into one of four sockets on the motherboard and are each designed to support a wide range of different radio frequency bands. Analog components on these boards upconvert, downconvert and amplify the IF signals to the desired RF and broadcast the output signal [13].
The daughterboard that we use in this paper is called WBX and it is a 50Hz to 2.2 GHz transceiver with applications in such transmission fields as DVB-T, GSM, or GPS[14].
2.2. Sensing System Software
Two options were considered as solutions for the developed prototype.
The first is called GNURadio, an open
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Differential Analysis of SDR Front Ends Table 1
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source framework for software radios. It provides the native application
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programming interface (API) for USRP2 platforms. Since it is easier to handle information flow graphically, GNU Radio offers with its application, GNU Radio Companion (GRC), the possibility to form a flow chart with graphical block elements.
This application provides numerous predefined blocks, organized in different groups like signal sources, signal sinks or modulation / demodulation functions [15].
Scenarios of Matlab to GRC interactions were implemented, as an indirect functional flow between Matlab and USRP2, with moderate success, however, because of GRC's limited development and functionality,.
When trying to develop a Software Defined Radio Sensing Prototype, Matlab, with its extensive DSP capabilities, is the software framework of choice. As of September 2010, Simulink - USRP2 interaction is natively supported by the newly launched Matlab 2010b.
Simulink's USRP2 Receiver block supports communication between Simulink and a USRP2 board, allowing simulation and development for various software-defined radio applications. The USRP2 Receiver block enables communication with a USRP2 board on the same Ethernet subnetwork [16].
This block receives signal and control data from a USRP2 board using User Datagram Protocol (UDP) packets. Although the USRP2 Receiver block receives data from a USRP2 board, the block acts as a Simulink source that outputs a column vector signal of fixed length and format (358x1). Some USRP2 parameters directly configurable through Simulink are central operating frequency, gain and decimation [16].
3. Experimental Setup and Results
As a proof of concept, for the proposed Sensing System architecture we have implemented a Radio Band Power Measurement System capable of performing a coarse Energy Detector sensing upon Digital Video Broadcasting - Terrestial (DVB-T) channels, by using apriori knowledge of the target signal characteristics (i.e. frequency, bandwidth).
The system is comprised of a USRP2 SDR platform, with its antennae and WBX daughterboard which stand for the SDR Hardware Platform from Figure1, and a 2.6 GHz (Intel Dual Core) processor, 2 [Gb] RAM memory, computer which is represented by the Host Computer block in Figure1. The computer's operating system is Linux Ubuntu 10.04 Lucid, while the specialized DSP specific software used is Matlab 2010b framework's Simulink. The latter two components constitute the System Software block from the general SDR based Sensing System architecture from Figure 1. For testing purposes and precision estimations, parallel measurements were carried out with a Signal Generator and a Vectorial Spectrum Analyzer (VSA) from Agilent Technologies. Also, for ensuring Simulink's compatibility with the USRP2 module, UDP protocol specific FPGA and Firmware images were used on the SDR platform.
3.1. Considerations about DVB-T
Channel Power Measurements
The System Software Block from Figure 1 is the core of the entire proposed Sensing System. It is here that all the radio spectrum data is collected by the SDR platform, ordered and interpreted according to the sensing algorithm. In this experimental implementation we have chosen to utilize the Energy Detector algorithm, which is, in fact, a Fast Fourier Transform (FFT) coefficient based, power measurement. In Figure 2, the Simulink functional flow of this process is shown.
The USRP2 Receiver block is where USRP2 functional parameters can be modified, even during execution. With the help of Slider blocks, Central Frequency, Decimation and Gain can be adjusted. The USRP2 block needs the broadcast static IP, 192.168.10.255.
In order to preserve an accurate and coherent graphic representation of the acquired signals the sample time has to respect the following implication:
ST is the Sample time, M is the decimation, and R is USRP2's ADC conversion rate.
In this case, as the decimation rate has a value of 12, the sample time will be 12e-8. The decimation value is restricted between a minimum of 4 and a maximum of 512, and needs to be a multiple of 4.
The elements of the USRP2 module's output vector are of type floating point with double precision, with 358x1fromat.
By implementing parameter values of: Gain = 0[dB]; Central Frequency = 646[Mhz]; Decimation = 12; we will get a 348x1 output vector that represents a frequency baseband of 8.33[MHz], with a central frequency of 646[MHz].
Parallel measurement, conducted with a VSA, revealed that 646[MHz] is the central frequency of an 8[MHz] DVB-T channel. This is the previously mentioned apriori knowledge of the sensing's target signal characteristics.
Because of the difference in bandwidth, between a DVB-T channel and the 0.33[MHz] gathered baseband, an additional “trimming” stage is necessary. The Rational Resampler block, in Figure 2 implements, alongside a specific Finite Impulse Response (FIR) filtering process, a resampling of the 8.33[MHz] baseband, with a fractional factor of 24/25, to the size of a DVB-T channel, 8[MHz].
Since the USRP2 vector's native format is 358x1, an unbuffer - buffer operation is required in order to have a. format. This is due to the fact that FFT blocks only accept power of 2 formats. Consequently, we will have an Unbuffer block, followed by a 2048Buffer block. The effect is that the signal vector, now has a format of 2048x1.
The Magnitude FFT block outputs the magnitude coefficients of the input signal by means of FFT. The subcomponents of the block can be further analyzed at [17].
The output is a number of 2048 squared
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FFT coefficients of the input signal
The resulting coefficients are utilized in computing the band power value [20] by using the authors' algorithm that is implemented in the Power custom block.
The determined Band Power value is then transformed into [dBm], decibels referenced to 1 [mW], in the block named dBm (Figure 3).
The following mathematical expression reflects the functionality of the dBm block:
where P is the power ratio expressed in watts and x is the power ratio in [dBm].
Parallel to the authors' Sensing System, an array of control power measurements were made by means of an Agilent 86900 high-precision VSA connected within the same subnetwork with the host, which communicates directly with a VSA block [9]. The test point was the output of the Buffer block (input of the Magnitude FFT block) from Figure 2.
Multiple measurements over the course of several days and over a variety of, bandwidths, spectral domains and conditions have proven that the results from the two scenarios differ by a maximum of 0.7%, which validates our prototype and our premises.
3.2. Power Measurement Algorithm
According to [5] band power is directly proportional with its magnitude. The Magnitude FFT block, computes 2048 FFT coefficients and squares them, in order to obtain the 2048 magnitude coefficients of an 8MHz frequency band. These parameters are passed then towards the input of the Power block. This is where the value of the DVB-T channel power is computed. Figure.3 portrays the functional flow of this block and its subcomponents.
As indicated by [10] an Agilent VSA (i.e. 35670A) computes the band power by summing up all the squared FFT coefficients, and dividing the sum to the effective bandwidth. The effective
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bandwidth is the result of the division of the frequency span to the number of FFT bins and subsequent multiplication by the window factor. The windows factor value is 1 for uniform windows, 3.82 for Flat-top windows or 1.5 Hanning.windows.
The authors used a formula similar to the one that Matlab uses to compute vectorial signals power [11]:
As a result of multiple tests and trials a fully functional optimized algorithm for computing the DVB-T channel power value was developed (Figure.3).
The first block after the input is a FIR filter, used for suppressing non-linearities related to the FFT squared coefficients. Next up, is a Sum block. The resulting sum is divided by the number of squared FFT coefficients, but also by 2 ( squared) as to obtain RMS values. A division by the value of the buffer is also necessary. A division by 50[Ohm], the value of a specific impedance, is the last step before finding the channel power value in [μW].
4. Conclusions and Future Development
In this paper the authors designed and developed a SDR based Cognitive Radio Sensing System with a very high functionality to cost ratio. The authors then proceeded to validate this prototype by implementing a Band Power Sensing System based on the concept of Energy Detector Sensing., which proved to provide significant added value from the functionality to cost ratio point of view, when compared to traditional sensing architectures and systems.
The implementation solution that the authors have opted for, was a functional flow based on the developed general sensing prototype. The chosen SDR platform was Ettus Reasearch's USRP2, while the DSP software opted for was Matlab 2010b's Simulink. It was in this software that the Energy Detector sensing functional core was implemented.
As further developments, the authors considered improving the Energy Detector sensing method from the functionality and precision point of view, by using methods such as channel discrimination by Wavelet Packet Decomposition or feature detection. This would be done with no additional hardware modifications to the prototype's architecture which is the quintessential advantage of using SDR platforms.
