Karuppanan P and Kamala Kanta MahapatraAbstract- This paper present a cascaded multilevel voltage source inverter based shunt active filter for power line conditioners (PLC) to improve the power quality improvement such as harmonics and reactive power compensation due to non-linear loads. The novel compensation control strategy is based on positive sequence voltage detector with generalized Fryze currents minimization, an approach different from conventional methods; the purpose is to guarantee linearity between the supply voltage and the compensated currents. The shunt active filter system is implemented with current controlled five-level cascaded inverter and it is connected to the distribution network for canceling current harmonics. The reference currents are extracted using the Fryze current minimization (FCM) algorithm. The cascaded multilevel active filter switching signals are derivates from proposed triangular carrier current modulator; it gives a good dynamic performance under transient and steady state operating conditions. This method maintains the capacitance voltage of the PWM inverter constant without any additional control circuit. The shunt APLC system is investigated and the performance parameters are obtained under various non-linear and unbalanced loads.
Index Terms- Shunt Active Power Line Conditioners (APLC), current harmonics, triangular carrier current modulator, positive sequence voltage detector, Fryze current control method.
INTRODUCTION
Harmonics and reactive power has become serious problems in power transmission and distribution system network. Non-linear loads such as rectifiers, switched-mode power supplies (SMPS), DC-motor drives, adjustable speed motors drives (ASDs), electric lighting and arc furnaces are responsible for originate the power quality (PQ) problems and prime sources of harmonic distortion [1-2]. The harmonic current is causing excessive heating, overloading and failure of capacitors, fuses, motors, transformers, lighting ballast and damages to sensitive electronic equipments and etc. Traditionally passive LC filters have been used to eliminate the current harmonics for power quality improvements; however in practical applications the passive filters introduce many disadvantages such as resonance, supply impedance dependant performance, large size and limited to fixed harmonic compensation [3-4]. To solve these problems of power-factor correction, many different configurations of static VAR compensators (SVCs) have been participated. Unfortunately some SVCs configurations generate lower-order harmonics themselves and the response time of some SVC configurations may be too long to be acceptable for fast-fluctuating loads. Active power filters (APF) or active power-line conditioners (APLC) are recently developed power-electronic equipment for solving these problems of current-harmonic suppression and reactive power compensation simultaneously [5-7]. The concept of shunt APF was introduced by Gyugyi and Strycula in 1976 [1]. The APLC has the ability to keep the mains current balanced after compensating regardless of either the load is non-linear and balanced or unbalanced [8-10]. The APLC can be connected in series for compensate the voltage distortion and in parallel for compensate the current distortion, but the series APF is not found in common practical use. Most of the industrial applications need current harmonic compensation, so the shunt filter is popular than series active filter [8-11].
The APF controllers determine in real time compensating current references and hence drive power converter. In 1932, S. Fryze developed new current control method; it's called the Fryze's power theory and it's used under distorted and/or unbalanced source voltages. In 1979 M. Depenbrock promoted the power analysis method based on the Fryze's power theory and its improving edition raised by F. Buchholz, so it was described as FBD (Fryze-Buchholz-Dpenbrock) method. FBD method is used in time domain and real-time system, and has the clear physical meaning [4]. In 1982, H.Akagi introduced instantaneous reactive power theory, but this arithmetic is rather complicated because this method includes Park transformation, dq transform and dq inverse transform [1]
This paper present a positive sequence voltage detector with generalized Fryze current minimization controller based cascaded shunt active filter for harmonics and reactive power mitigation of the non-linear loads. The cascaded multilevel H-bridge active power filters has been widely used for power quality applications due to increase the number of voltage levels, low switching losses, low electromagnetic compatibility for hybrid-filters and higher order of harmonic elimination. The cascade M-level inverter consists of (M-1)/2 H-bridges and each bridge has its own separate dc source [9-15]. The cascaded inverter gate switching signals are generated using triangular carrier current modulator; it provides a dynamic performance under transient and steady state operating conditions. The reference currents are extracted using Fryze current minimization method. This method maintains the dc-side capacitance voltage of the cascaded multilevel voltage source inverter constant without any additional controller circuit and it takes less time to settle. The shunt APLC system is investigated using extensive simulation and the result proof that the active filter is improving the power factor and stability of distribution grid.
Design of shunt APLC system
Cascaded active filter for power line conditioning system is connected in the distribution network at the point of common coupling through filter inductances and operates in a closed loop. The three phase active power filter comprises of 24-power transistors with freewheeling diodes, each phase consist of two-H-bridges in cascaded connection and every H-bridges having a dc capacitor. The shunt APLC system contains a cascaded inverter, RL-filters, a compensation controller (positive sequence voltage detector with generalized Fryze current minimization controller) and switching signal generator (triangular carrier current controller) as shown in the fig 1.
24
isa*,isb*,isc*
isa,isb,isc
ica,icb,icc
Rs,Ls
Fryze current minimization control
Current
Sensor
CDC
iLa, iLb, iLc
RL
LL
Non-sinusoidal Load
3-phase supply
Triangular carrier Current Controller
Cascaded VSI
Positive sequence voltage detector
Voltage
Sensor
Current
Sensor
N
Unbalanced load
RL, LL
Fig 1 shunt active power line conditioners system
The three phase supply source connected to the non-linear load; the instantaneous source current is represented as and the instantaneous source voltage as. The nonlinear load current will have a fundamental component and harmonic current components, which can be represented as
If the active power filter provides the total reactive and harmonic power, will be in phase with the utility voltage and would be sinusoidal. At this time, the active filter must provide the compensation current; The Current harmonics is achieved by injecting equal but opposite current distortion components at the point of common coupling, there by canceling the original harmonic and make sinusoidal in the supply source that improving the power quality on the connected power distributed system.
A) Power Converter:
Cdc
Cdc
C
B
A
Fig 2 Cascaded multilevel voltage source inverter based active power filter
A cascaded multilevel active power inverter is constructed by the conventional of H-bridges. The three phase active filter comprises of 24-power transistors and each phase consists of two-H-bridges in cascaded method for 5-level output voltage, shown in fig 2. Each H-bridge is connected a separate dc-side capacitor and it serves as an energy storage elements to supply a real power difference between load and source during the transient period. The capacitor voltage is maintained constant using PI-controller and the output voltage is. The 24-IGBT switching operations are performed using proposed triangular carrier current modulator and harmonics is achieved by injecting equal but opposite current harmonic components at point of common coupling.
B) Positive sequence voltage detector:
PLL
Synchronizing circuit
Vsa
Vsb
Vsc
ia1
ib1
ic1
va1
vb1
vc1
R
Fig 2 block diagram of positive sequence detector
The time domain based fundamental positive sequence voltage detector is the most frequent techniques in terms of minimized voltages shown in fig 2. It's to perform under non sinusoidal voltages and unbalanced current conditions. The phase voltages at the load terminal consists of the positive sequence component that containing negative and zero sequence at fundamental frequency and also harmonics from any sequence component. The detection of the fundamental positive sequence and Fryze current minimization control strategy makes the shunt APLC to compensate load currents, so that positive sequence detector produce real power only which is supplied by the source. A novel positive sequence detector developed with the PLL (Phase- Locked-Loop) for locked to the fundamental frequency of the system voltages and simple additional algebraic manipulation of the measured voltages. The PLL circuit tracks continuously the fundamental frequency of the measured system voltages. The PLL design should allow proper operation under distorted and unbalanced voltage waveform. The PLL-synchronizing circuit shown in fig 3 determines automatically the system frequency and the inputs are line voltages and. The outputs of the PLL circuit are the three phase currents. This algorithm is based on the instantaneous active three-phase power expression, it's written by
The current feedback signals and is built up by the PLL circuit and time integral of output calculated of the PI-Controller. It is having unity amplitude and lead to 1200 these represent a feedback from a positive sequence component at frequency. The PLL circuit can reach a stable point of operation when the input of the PI controller has a zero average value () and has minimized low-frequency oscillating portions in three phase voltages.
Sin (ωt - π/2+2π/3)
Sin (ωt - π/2 - 2π/3)
Sin (ωt - π/2)
Sin (ωt)
Sin (ωt+2π/3)
PI
Controller
Vab
Vcb
∑
ia1
ib1
ic1
Fig 3 synchronizing PLL circuit
Once the circuit is stabilized, the average value of is zero and the phase angle of the positive-sequence system voltage at fundamental frequency is reached. At this condition, the currents become orthogonal to the fundamental positive-sequence component of the measured voltages. The PLL synchronization output currents are defined as
Therefore the PLL output current signals and the distorted/unbalanced voltages of the power supply are measured and which are in phase with the fundamental component. The PLL allows the use of a dual expression for determining active voltages and to extract the positive sequence component from. Therefore the signals are three symmetric sine functions with unity amplitude, which correspond to an auxiliary fundamental positive-sequence current that is in phase with positive-sequence voltage. So the average value of the three-phase instantaneous power should maximum and the average signal comprises the total amplitude of positive-sequence voltage.
The positive sequence voltages are calculated from the following equations
Therefore, it is possible to guarantee that the signals are sinusoidal and have the same magnitude and phase angle of the fundamental positive-sequence component of the measured system voltage. Then the output of these positive-sequence voltage involve the Fryze current minimization algorithm for determine the reference current.
C) Fryze current minimization algorithm:
Low-Pass
Filter (LPF)
Reference Current Calculation
Active Fryze
Conductance
Calculation
Active Current Calculation
va1
vb1
vc1
iLa
iLb
iLc
isa*
isb*
isc*
iwa,iwb,iwc
Fig 4 block diagram of generalized Fryze current minimization algorithm
The generalized fryze current method presents a minimum rms value to draw the same three phase average active power from the source as the original load current shown in fig 4. This reduces the ohmic losses in the transmission line and to guarantee linearity between the supply voltage and compensated current. The instantaneous equivalent conductance is calculated from the three phase instantaneous active power.
Moreover the root mean square (rms) aggregate voltage is derived from the instantaneous value of phase voltages, it's given as
The conductance or admittance is represented by an average value instead of a varying instantaneous value. The instantaneous conductance calculated from the three phase instantaneous phase voltage calculated from the positive sequence voltage detectorand load current. It's derived the following equation
The average conductance passing through Butterworth design based low pass filter (LPF). The LPF cutoff or sampling frequency assign 50 Hz fundamental frequency that allows only the fundamental signal to the active current section. The instantaneous active current of the load current are directly calculated by multiplying by phase voltage respectively and are defined as
The desired reference source currents calculated from the active current, after compensation, can be written by
Here is root mean square line current and the magnitude is unity. The control strategy indicates that shunt APLC should draw the inverse of the non active current of the load and the results shown compensated currents are proportional to the corresponding phase voltage.
D) Hysteresis current controller (HCC):
The proposed triangular carrier current modulator for active power filter line currents can be executed to generate the switching pattern of the cascaded voltage source inverter. There are various current control methods proposed; but the triangular carrier current control method has the highest rate for cascaded active power filters. These inverters features are quick current controllability, the switching operation induced the suppression of the harmonics, the average switching frequency of each inverter is equality and unconditioned stability. The five-level voltage source inverter systems of the current controller are utilized independently for each phase. Each current controller directly generates the switching signal of the three A, B, C phases. The A-phase actual source current represented as Isa and reference current represent as Isa* as shown in fig 3, similarly derived the B and C phase currents.
Isa
Isa*
Kp
1
0.5
0
-0.5
0
.
0
0.5
G1
G2
G3
G4
G5
G6
G7
G8
Fig 5 Proposed triangular carrier current controller
To determine the switching frequency by means the error current [desired reference current compare with the actual source current] multiplied the proportional gain (Kp) and compared with triangular carrier signal. The four triangular signals are generated same frequency with different amplitude for cascaded inverter. Thus the switching frequency of the power transistor is equal to the frequency of the triangular carrier signal. Then, the output signal of the comparator is sampled and held D-Latch at a regular interval synchronized with the clock of frequency equal to. Note that 12-external clock applied to each converter andis set as 30 ns, because each phase in one converter does not overlap other phase. Therefore the harmonic currents are reduced as if the switching frequency were increased. The active power filter suppresses the harmonics caused by the switching operation of the cascaded inverter.
Simulation result and analysis
The performance of the proposed control strategy is evaluated through Matlab simulation using Simulink tools in order to model and test the system under balanced/unbalanced non-linear load conditions. The system parameters values are; Line to line source voltage is 440 V; System frequency (f) is 50 Hz; Source impedance of RS, LS is 1 Ω; 0.5 mH; Filter impedance of Rc, Lc is 1 Ω; 1.3 mH respectively; Diode rectifier RLLL load: 20 Ω; 200 mH respectively; Unbalanced three phase RL load impedance: R1=10 Ω, R2=50 Ω, R3=90 Ω and 10 mH respectively; DC side capacitance (CDC) is 1100 μF; Power devices build by IGBT with Diodes.
The nonlinear or non-sinusoidal diode rectifier RL load connected with ac main network and active power filter connected in parallel at the point of common coupling for decompose the harmonics and reactive power. The diode rectifier R L load parameter values 20 ohms and 200 mH respectively. The simulation result of source current after compensation is presented in fig 6 (a) that indicates the supply current is sinusoidal. The six-pulse diode rectifier load current or source current before compensation is shown in fig 6 (b). The desired reference current is extracted from our proposed Fryze current minimization method that is shown in fig 6(c). The shunt active power filter supplies the compensating current or filter or harmonic current that is shown in fig. 6(d).
(c)
(d)
(b)
(a)
Fig.6 Simulation results for 3-phase APLC under non-linear load condition (a) Source current after active power filter compensation (b) Load currents or source current before compensation (c) Reference currents by Fryze current control algorithm and (d) Compensation current by active filter
The three phase unbalanced RL load connected parallel with the diode rectifier load in the three phase main network. The unbalanced load condition studied and simulated with active power line conditioners. The three phase unbalanced RL load current or source current before compensation is shown in 7 (a). The source current after compensation is presented in fig 7 (b) that observed the current is becomes sinusoidal. The shunt active power filter supplies the compensating current that is shown in fig. 7(c). We have additionally achieved power factor correction as shown in fig 7(d) that indicate a-phase voltage and a-phase current are in phase the line.
(c)
(d)
(a)
(b)
(d)
Fig.7 Simulation results for 3-phase shunt APLC under non-linear with unbalanced load condition (a) RL Load current or Source current before compensation, (b) Source current after active filter compensation (c) harmonic current by active filter and (d) unity power factor correction.
The capacitance voltage (Cdc) and its settling time are controlled by fryze current minimization controller itself, without any external controller circuit. This controller reduces the ripple voltage to certain level and makes settling time to a low value in both non-linear and unbalanced load condition; it's plotted in fig 8 and measured the settling time.
Fig 8 the DC side capacitor voltage settling time (t= 0.027s) is same both non-linear and non-linear with Unbalanced load
The Fast Fourier Transform (FFT) is used to measures the order of harmonics with the fundamental frequency 50 Hz at the source current, as shown in fig 9
(b)
(c)
(a)
Fig 9) Order of harmonic (a) under the non-linear load condition source current without active power filrer (THD=24.983 %), (b) Under the non-linear condition with active filter (THD=3.49 %) and (c) under the unbalanced load condition source current with APF compensation (THD=3.09 %).
The positive sequence voltage detector with generalized Fryze current minimization control based compensator filter made sinusoidal source current in the supply. The total harmonic distortion measured and compared, shown in table 2.
Table 2 FFT analysis of Total harmonic distortion (THD)
Condition(THD)
Source Current(IS) without APF
Source Current(IS) with APF
Non-linear load only
24.98 %
3.49 %
Non-linear with unbalanced load
20.66 %
3.09 %
Power factor
0.9177
0.9998
The simulation is done various non-linear and non-linear with unbalanced load conditions. The obtained result shows the source current and load current is small variation in balanced and unbalanced conditions. FFT analysis of the active filter brings the THD of the source current less than 5% into compliance with IEEE-519 standards.
Conclusion
The investigation demonstrates that positive sequence voltage detector with generalized Fryze current minimization control strategy can facilitate improving the power quality. This control method extracts fundamental (reference) components of the source current from nonlinear loads. The shunt APLC system is implemented with three phase current controlled cascaded multilevel voltage source inverter; it has filtered current harmonics and compensated reactive power. The cascaded inverter gate control signals are derived from proposed triangular carrier current controller. The positive sequence voltage detector with Fryze approach additionally maintains the capacitor voltage of the cascaded inverter nearly constant without any external control circuit. The shunt APLC in conjunction with the proposed controller performs perfectly under unbalanced non-linear load conditions. Important performance parameters are plotted. This approach revealed that THD of the source current to be less than 5% that is in compliance with IEEE-519 standards.
