The power amplifiers are one of the most important components in wireless communications, and it is the main contributor in the overall power consumption in the transmitter systems, from here that is desirable to achieve a good PAE that will increase the lifetime of the power source that for satellite communications consists in batteries and solar energy systems.
In this thesis is presented the design of a 1W power amplifier for TTC transmitters, this project has grown as a cooperation between Norspace in Horten, Norway and the Microwave Electronics Laboratory at Chalmers University. An initial design using MMIC technology is developed, the specifications are shown in the Table 0 .1. Power amplifier specifications A special care of the junction temperature in the channel of the transistor should be taken, as it is known, the reliability of the device depends mainly of this heating, an analytical analysis [1] is implemented for this purpose integrating this calculation in the CAD design optimization.
Another design with discrete components and in thin-film technology is presented for fulfill the same specifications as de MMIC case. The results obtained in the simulations and measurements for both designs are compared.
TT&C Transmitters
Although the satellite communications links are designed for a period of many years they require constant supervision and intervention, even under normal operation. The telemetry, tracking and command (TT&C) systems is the communication interface between the satellite and the base station, giving to the ground operators the mission payload and the maintenance data from the satellite, at the same time provides to the operators the capacity to control and operate many functions. The TT&C subsystem tasks are mainly:
Command: reception and detection of control orders from the ground base station
Telemetry: modulation and transmission of data on board
Tracking: Range determination, distance and speed measurements
All these functions should be reliably operating to accomplish the spacecraft mission for that different constrains limit the TT&C system, one of them is the power source that most of times come into batteries and solar or thermoelectric generators. Other constrains is the mass and size limitations and it is a task for the designer to develop a system that improves the overall performance of the spacecraft and the mission. [2]
In the TT&C system the power amplifier is located at the output of the transmitter connected to the antenna, it plays a very important role in the reliability and the lifetime in the spacecraft mission, as vital conditions are controlled by its proper operation, a failure or temporal loss of the TT&C system could imply the end of the spacecraft.
Thesis Outline
In the second chapter of this thesis a general power amplifier theory is described showing the traditional classes, its advantages and disadvantages. In the third chapter is explained the MMIC technology, the different processes and its applications for power amplifiers. Also details are given for the treatment of the junction temperature. In the last part the conclusions of both designs and its comparisons and suggestions of the author for future developments of TTC transmitters.
Power Amplifiers
During the history of RF power amplifiers, a lot of efforts have been given in order to get an efficient amplification, different classes of amplifications have been presented including the switching mode amplifiers, each one presenting its advantages on efficiency and linearity. However, different design methods have been proposed, and it worth to note that power amplifiers design differs from small signal amplifiers in the way the output is matched.
In small signal the target is to reach the maximum stable gain, for that the output of the transistor is matched with the complex conjugate of the impedance in the output plane. The design method for small signal amplifiers is based on the S-Parameters of the transistor that are related to a specific bias point [3]. In power amplifiers the matching is done in order to get the highest output power possible, even when the gain is reduced as shown in the Figure 1.3 .1.
Figure 1.3.1 Power Matching Vs. Gain Matching
Load Pull
The more accurate way to find the optimal load required at the output of the transistor is using the load-pull simulation. In early works, the load pull measurement was done in real devices using tunable sources and impedances in the input and output of the transistor, once the maximum power was reached the corresponding impedances were measured taking into account the effect of the TRL fixture, also a principal problem of the setup was that not always were available a fixture for the desired frequency and many load-pull kits were necessary in order to work in different frequencies that is very costly. Nowadays, the load-pull method can be implemented in the different CAD software created for microwaves engineering, the accuracy of this procedure depends directly of the model used for the transistor.
In the simulation different frequencies are available and can be shown directly the delivered power, the harmonics components, and the efficiency for the corresponding impedance in the smith chart giving great advantage and simplicity to the method, comparing to the real one.
Load Line
In the case of a HEMT power amplifiers an initial prediction of the output impedance for reach the highest output power is found from the I-V characteristic curve of the transistor, as shown in Figure 1.3 .2, the Knee and Breakdown voltages are represented by the left and right dashed lines respectively, while the load line for high output power is showed with the diagonal red line, from the graphic the optimum load is given by the so called Cripss method [4]:
(1.3.0)
As an example in the Figure 1.3 .2 the breakdown voltage () is 8V the knee voltage () 0.9 V and the maximum current () is 0.5A then the optimum load is 14.2ð®.
Figure 1.3.2 HEMT I-V curves and loadline
Stability
Not every impedance is suitable for matching due to stability issues, in the smith chart the stability is reflected as the reflection coefficients should be smaller than one. The stability can be seen through the k-factor [3], when this factor is greater than one the transistor is unconditionally stable and any impedance of the smith chart is suitable for matching.
( 1.3.0)
Where
(1.3.0)
When the k-factor is smaller than one there is an area on the smith chart that should be avoided, this area corresponds to the stability circles, that can be calculates with the following equations, where Cs and Cl are the centers of the circles and Rs and Rl their corresponding radius.
( 1.3.0)
( 1.3.0)
( 1.3.0)
(1.3.0)
Note that these expressions are made with the S-Parameters of the transistor, and so they describe the stability for a specific bias point, but if the signal to be amplified is large the sweeping in the input of the transistor should be taken in to account when analyzing stability, a few S-parameters corresponding to biasing points in the range of the sweeping of the transistor would determine more accurate the stability region of the transistor.
Efficiency
One of the most desired requirements in a power amplifier is to get a high efficiency as it results in an extended battery lifetime and easier thermal dissipation, some ways to measure the efficiency of an amplifier have been defined. The drain efficiency is the ration between the output power and the DC power:
(1.3.0)
Sometimes is desired to include the level of in input signal of the amplifier, or the related gain, so the Power Added Efficiency (PAE) is defined as the ratio between the gain and the DC power
(1.3.0)
The cases when the amplifier gives a low gain the drain efficiency could be high but the PAE will be much lower, is always good to have an insight of both figures of efficiency to determine a good behavior of the amplifier.
Power Amplifier Classification
The traditional classes are characterized by the reduction of the conduction angle, it depends on the bias point of the transistor in the I-V curve and the loadline. Classes A, B C, and AB will be explained in detail in the next sections, and a general overview of the high efficiency switch mode amplifier will be given also.
Class A
The class A amplifiers are recognized for its strongly linear response, the output current waveform is ideally sinusoidal or in other words the conduction angle is 2À, see Figure 2.2 .3. This behavior is achieved due to a bias point located in the middle of the loadline in the Figure 1.3 .2, the swing over the input of the transistor makes it to move across the linear region avoiding the saturation or the pinch off point.
The principal advantage of the class A amplifiers is the linearity of its response but the cost of it is a low efficiency, the DC consumption is due to the bias point Vmax/2 times Imax/2 and the RF power will be ½ times Vmax/2 times Imax/2 and according to the equation ( 1.3 .0) the drain efficiency yields in 50%.
Figure 2.2.3 Class A Waveforms
Class B
In class B the Amplifier is biased on the pinch off, the load line is described in Figure 2.2 .4, so only the half of sine wave will be conducted. The gain is approximately 6dB reduced in comparison to class A amplifiers. In class B the output is not a pure sinusoidal wave as show in the Figure 2.2 .5 it corresponds to a half wave rectification, it should be noted that due to its symmetry only the even order harmonics are suppressed and the odd orders will be present at the output, Nevertheless is practical to terminate in a short circuit the second harmonic to prevent saturation and power dissipation and keep a high efficiency in the fundamental [5]
Figure 2.2.4 Bias point for Class B operation
The efficiency of the Class B is higher as only half of the cycle is conducted, the DC consumption is due to the bias point Vmax/2 times Imax/À and the RF power will be ½ times Vmax/2 times Imax/2 and according to the equation ( 1.3 .0) the drain efficiency yields in 78.6%.
Figure 2.2.5 Class B Waveforms
Class AB
The class AB amplifiers are biased on a drain current less than half of the maximum value, the angle conducted is between 180 and 360 degrees, see Figure 2.2 .6, commonly is used in a point close to the pinch off voltage, this configuration is called the “deep ABâ€. The level of the odd and even harmonics depends directly on the conduction angle, in the Figure 2.2 .7 are shown the DC components, the fundamental and the harmonics for different conduction angles including the class C region[4] The Harmonics are exactly zero for class B but in class AB they can not be neglected, also it worth to note that the fundamental component in the class AB region is higher than the class A but when the conduction angle approaches À the fundamental reaches the same level than the class A operation, in other words in Class B and AB the efficiency is higher as the fundamental is higher and the DC consumption lower but the output termination and the voltage waveform should be considered.
Figure 2.2.6 Class AB Waveforms
Figure 2.2.7 Harmonic analysis for different conduction angles
The efficiency and output power can be analyzed analytically for different angles:
( 2.2.0)
the results are shown in Figure 2.2 .8, can be appreciated the relations explain previously regarding the fundamental level in class AB region, The Class B operation is an interested point as it offers the same output power than Class A, suppression of the odd harmonics and a high efficiency, increasing the reduction toward the class C operation is accompanied by a considerable reduction of the output power.
Figure 2.2.8 RF Power and Efficiency as a function of conduction angle
Class C
Class C amplifiers reduces the angle of conduction to less than half of the cycle, Figure 2.2 .9, in theory with an angle of zero the efficiency would become 100%, but also the gain and the output power go to zero at that level of efficiency and a higher level of non linearity effects are present. The efficiency and the drawback of the output power while reducing the conduction angle have been already explained and can be seen in detail in the Figure 2.2 .7 and Figure 2.2 .8
Figure 2.2.9 Class C Waveforms
Switched mode amplifiers
Switch mode power amplifiers (SMPA) take the transistors as power switches, during the on cycle the device acts as a short circuit and no voltage should be across it, meanwhile during the off cycle it behaves as an open circuit and no current should flows through it. The classification between the different SMPA classes (E, F, and D) is made according to the way the output is tuned at various harmonic frequencies. In general, SMPA’s exhibits low gain but very high efficiencies, theoretically a PAE of 100% is achievable.[6].
Other classes are the H and G that use a modulated signal in the output bias, these configurations uses bias points as the class A or B, it allows them to offer a good linearity and a good efficiency.
Doherty amplifier
The fundament of the Doherty amplifier is to have a load which resistance could change dynamically according with the input level so a higher efficiency can be maintained during the whole cycle. This effect has been performed by using 2 separate transistors simultaneously what is called the Doherty amplifier [4]. The second auxiliary transistor applies current to the load at certain levels of input power, seen from the main transistor, it seems as the resistor has changed it resistive characteristic and the final output power results in the combination power of both transistors. In few words, when an input signal is small just the main transistor is working in his lineal region, when the signal increases the auxiliary transistor compensates the nonlinear effects of the main transistor keeping a higher power level and improving the efficiency, it can be illustrated betted in the Figure 2.2 .10
Main
Auxiliar
Input
Main
Auxiliar
Combined
Power in
Power out
Output
Figure 2.2.10 Doherty Schematic and performance
So far the Doherty configurations gives many advantages and it has been used more often in the last years but its mainly constrains are the linearity and the bandwidth that should be considered depending on the application to be used.
Overdriven class A amplifier
For TT&C and applications often is found a overdriven or saturated class A amplifier, this kind is characterized due to a Class A bias point but an input signal that overpass the level of saturation and cutoff of the transistor. as it was described previously, this effect generates harmonic components in the output signal due to the strong non linear response.
The load is typically of the same value than the Class A amplifier and the harmonic components would be filtered out by subsequent circuitry. The efficiency that can be obtained from such amplifier depends directly in the overdriving level, at 1dB compression point about 63% can be reached theoretically, at 3dB compression 71% and a maximum of 81% is possible when the response tents to a square wave form. [4]
In order to reach higher efficiency is necessary to sacrifice the power gain and linearity capabilities of the circuit, this limits the overdriven amplifiers to applications with low sensitivity to amplitude distortion.
Push Pull Amplifier
The push pull architecture as the Doherty, are techniques that were created in the early time of the vacuum tubes electronics and now are been applied in the semiconductors age. The push pull was motivated by audio amplifiers, where is not acceptable to transmit with a reduced conducted angle. In general, it consists in 2 transistors in parallel where one of them is driven differentially so the positive cycle is amplified by one of the transistor and the negative cycle by the other, having only 1 transistor conducting at anytime, each wave is added to reconstruct the signal in the load.
Figure 2.2.11 Rf Push Pull Amplifier
Negative Cycle
Balun
Balun
Positive Cycle
Input
Originally it was thought for audio applications but it is also used in some RF designs, specially in broadband amplifiers. Tin the RF push pull amplifier the differential drive is made with baluns that provides the out of phase of the input signals as shown in the Figure 2.2 .11, it has another advantage, as the input signals are equal in magnitude but opposite in phase, there will be cancelation in the feedbacks leaks. However in the microwave region of GHz some problems might appear, mainly the techniques used for grounding of microwaves circuits, through viaholes and the distributed nature at this frequency range degenerate the symmetry of the push pull configuration creating affecting the gain and the cancelation described previously. In addition, the baluns for microwave push pull amplifiers are not an easy task, it involves high power management, phase and amplitude balance and negligible insertion loss.
A possible solution for these difficulties is the using of lumped elements to design the baluns, however it requires the availability of precise simulation models for capacitor and inductors. Even when the push pull configuration has a very good performance it has been described its problems that need a preliminary development effort focused in the baluns and its phase and magnitude balance.
MMIC technology
Overview
A Monolithic Microwave Integrated Circuit (MMIC) consists in a circuit that is fabricated over the same semiconductor substrate and it is designed to work on the microwave frequencies region that is considered from 300 MHz to 300 GHz.[7] All the active, transistors, and passive components, resistors, inductors and capacitors including all their interconnections are built in within the integrated circuit.
Different applications have found suitable the MMIC technology for their development due to its high frequency and low noise performance, is common to find MMIC in different wireless systems applications as mobile cellular networks, GPS receivers, WLAN networks, military and space applications and also a growing field in vehicle and traffic systems. [8][9].
The MMIC have been preferred over the conventional MIC (Microwave Integrated Circuit), which consists in hybrid circuits with discrete active devices and passive components soldered on a common substrate. The MMIC advantages and disadvantages are summarized in the Table 3.1 .2
Table 3.1.2 MMIC and MIC comparison
MMIC
MIC
Economical for complex circuits and large production volume
Cheaper low complex circuits that can be automatically assembled
High reproducibility
Lower reproducibility due to wires and placements.
High Reliability
Reliability suffers from mechanical connections
Low parasitic effects offering higher frequencies and more bandwidth
Specialized discrete transistors for special applications can be found with better performances
The area should be reduced as much as possible to keep a economic result
The substrates are cheap, and larger areas can be used
Smaller and lighter suitable for mobile applications
Bigger and heavier more suitable for station applications
Long time process (3-6 months)
Can be done within 1-2 weeks
Expensive equipment is required
Little capital is required for a start up
The space industry has adopted MMIC designs for many applications, especially on board circuits are required to be small, light and efficient. The transporting operation is very expensive and also has unique environmental conditions, during the launch the circuits are exposed to very high vibrations, intensive noise and sometimes electromagnetic interferences. During the operation these circuits have limited amount of energy and there is no possibility of field repair what demands a high reliability. Due to the special conditions of the space industry applications the MMIC technology have been applied to many devices as, voltage controlled attenuator, variable gain amplifiers, up/down converters, LNA’s, mixers, LO’s and power amplifiers. [10]
Substrate
The final performance of the MMIC is very depended on the process selected for the application. One of the initial decisions to be done is the substrate material to be used. The frequency respond depends on the mobility of the electrons in the doped semiconductor and the transistor breakdown voltage in the energy band gap. The most common used substrate are silicon (Si) and Gallium Arsenide (GaAs), other substrates used are Silicon carbide (SiC), Indium phosphide (InP) and Gallium Nitride (GaN).
Silicon have been used widely due to it is the most economic, but GaAs offers better performance on millimeter wave frequencies, Si devices are pushing to reach frequencies performance comparable to GaAs with the addition of a silicon germanium (SiGe) layer, nevertheless, GaAs dominates in the microwave range, also its high resistivity make it more suitable for passive components. InP devices are developed for higher frequencies beyond 100GHz. SiC and GaN are competing in applications that handle high power as they have a very wide band gap. Some of the semiconductor characteristics for the most common substrates are summarized in the Table 3.2 .3 [11]
Table 3.2.3 Most common semiconductor Properties
Material
Electron Mobility (cm²/Vs)
E-gap(eV)
Si
900-1100
1.11
SiGe
2000-3000
0.85
SiC
500-1000
2.86
GaAs
5500-7000
1.43
GaN
400-1600
3.4
InP
10000-12000
1.35
Bipolar Transistors
Another decision to be done is the type of transistor, in a simple level this choice is reduced between FET or bipolar transistor but there are many types involved in these 2 groups
N
P
N
Figure 3.3.12Bipolar transistor representation
The bipolar transistor operates with positive voltage in the collector and the emitter is grounded so the current flows from collector to emitter, this current is controlled by the voltage between base to emitter, when it is zero no current can flow and when the base-emitter voltage is greater than the activation level, around 0.7V, the current can flow.
The bipolar transistor is a three terminal device with base, emitter and collector terminals. The emitter-base-collector consist of a p-n-p or n-p-n junctions, creating the p-n junctions that activates the transistor operation as shown in the diagram in the Figure 3.3 .12
Some of the bipolar transistor subclasses are the silicon bipolar and the hetero-junction bipolar transistors (HBT)
Silicon bipolar transistor
The silicon bipolar transistor is the traditional bipolar device, where the three regions correspond to 3 different doping levels over the same substrate, in this case silicon. The operation is based in the interaction of the two p-n junctions (see Figure 3.3 .13) The emitter-base junction is forward biased while the collector-base is reversed biased, the base is designed to be small enough to allow the electrons injected to in the emitter reach the collector.
Figure 3.3.13 Bipolar transistor cross section [8]
The deplection zones created in the p-n junctions generates intrinsic capacitances that governs the frequency response of the device, through an analysis [8] can be seen that for higher frequencies are needed a large base doping concentration, a narrower base and a large gain. These required physical characteristics have conflicts as for a large gain it is necessary to reduce the doping level and other strategies should be studied for improve the frequency response of the bipolar transistor.
Hetero-junction bipolar transistor
In order to get higher frequencies than the silicon bipolar transistor and with the constrains of size and performance a transistor with a base-emitter junction conformed by two different semiconductor materials, common materials used are Si emitter with a SiGe base, AlGaAs or InGaP emitter with GaAs base and ÃÅ’nP emitter with InGaAs base. The hetero-junction allows to reduce the base resistance and therefore the transit time of the electrons and increase the frequency of the device. A cross section of the AlGaAs HBT is shown in the Figure 3.3 .14
Figure 3.3.14 AlGaAs HBT cross section [8]
Each of the semiconductor combinations mentioned here has different uses and applications, they are summarized in the Table 3.4 .4 .
Field Effect Transistors (FET’s)
The FET transistor are usually biased with positive voltage in the drain and the source is grounded, so the current flows from drain to source, this current is controlled by the voltage between gate to source, when it is zero the current can flow and when it reaches a negative level around -5V, no current can flow.
D
S
Figure 3.4.15 FET representation
Different than the bipolar transistor in FET’s the current flows across the surface of the substrate passing under the gate contact in the Figure 3.4 .15 only one gate is represented by the thin rectangle between drain and source but in general and specifically power devices are built with many gate fingers and drain and sources interconnected.
Some of the FET subclasses are the metal semiconductor field electric transistor (MESFET) and the high electron-mobility transistor (HEMT)
MESFET
The GaAs MESFET was the first three terminal RF device. In general it has two ohmic contacts for the drain and the source and a metal-semiconductor Schottky contact in the gate, as shown in the Figure 3.4 .16
Figure 3.4.16 MESFET cross section[8]
During the operation the current flows from source to drain across the channel under the gate, due to the inferior mobility of the holes the carrier are electrons and so the channel is n-doped. The frequency response is depended on the intrinsic gate capacitance and resistances, for increase the frequency it is necessary to have a shorter gate.
HEMT
The high electron mobility transistor operates in a very similar way to the MESFET but the HEMT uses a vertical architecture using different layers to create a channel where the electrons are separated from their donors, it yields in higher mobility of the electrons improving the noise and gain characteristics of the device. One of the most used configurations is the AlGaAs/GaAs HEMT shown in the Figure 3.4 .17 where the n-doped and undoped AlGaAs layers conform the high mobility channel.
Figure 3.4.17 HEMTcross section[8]
Some variations of the HEMT are the pseudomorphic GaAs, the lattice matched with pseudomorphic InP Hemt and the metamorphic GaAs, there are brief descriptions of these specific cases in the literature [8]
After describing some of the principal technologies in bipolar and electric field transistors characteristics for the different cases are summarized in the Table 3.4 .4:
Table 3.4.4 MMIC Processes and applications
Technology
Comments
Si Bipolar
Low power applications
SiGe HBT
Good Noise figure, low output power. Used in oscillators, mixers and LNA
GaAs HBT
Very high gain and linearity, high parasitic effects, high power and efficiency, High noise figure. Used in Oscillators, mixers, LNA and Power Amplifiers
InP HBT
Very High Frequency, medium output power.
Silicon CMOS/BiCMOS
Used in digital analogue circuit integrations
GaAs MESFET
Low noise figure, medium output power, good linearity, easy fabrication
GaAs pHEMT
High transconductance, complex fabrication. Used in LNA and Power Amplifiers
InP HEMT
Very high frequency, Fragile, medium output power. Used in oscillators, mixer, LNA and Power Amplifiers
GaN FET
Highest Power densities, and PAE
MMIC Power Amplifier design considerations
Steve Marsh has presented [9] a decision diagram for the MMIC process suggested according to the frequency and output power required (Figure 3.5 .18).
Figure 3.5.18 MMIC process decision diagram[9]
In the decision diagram and according to the characteristics described in the Table 3.4 .4 and Table 0 .1 shows the GaAs pHEMT and HBT technologies are suitable for the application of this work. After a searching with some principal MMIC foundries [12][13][14][15][16] can be concluded that a pHEMT GaAs process would be ideal, in order to reach the output power level desired it is necessary that the process offers a 0.20µm process. When it refers to a space application the reliability is a fundamental point, it is recommended to operate the device at de-rated conditions respect to the process ratings provided by the foundry [17], and it is proper to choose a larger gate process as 0.25µm or 0.35µm which ones give about 1 W/mm.
The process selected due to its performance and availability is the PPH25X from United Monolithic Semiconductors [16] that is a specified power process with the characteristics described in the Table 3.5 .5
Table 3.5.5 UMS PPH25X process specifications
Active Device
pHEMT
Power Density
900mW/mm
Gate Length
0.25µm
Ids (gm max)
Ids (sat)
170mA/mm
450mA/mm
Vbds/Vbce
>18 V
Cut off Freq.
45 GHz
V Pinch
-0.9 V
Gm max
400mS/mm
It worth note that the selected process have already been successfully evaluated by the European Space Agency for space qualified applications.
Taking into account the theory explained in the Chapter , is desired to develop a high efficiency amplifier, it will allow also avoiding an overheating in the channel and increase the lifetime specification of the device. Some of the high efficiencies configuration explained presents some disadvantages and difficulties in the working frequencies regarding, bandwidth, design, fabrication. Another limitation we should consider is the cost, when designing a MMIC circuit the area and dimensions play an important, more than in the MIC circuit where the substrate is cheaper and easy to dispose and the budget is mainly use in the active discrete components, but in the monolithic solution should be avoided the wide use of distributed elements, when the frequency is in the low GHz. range some of them can become a bit big in terms of area usage what will increase considerably the costs of the circuit.
For the case of this work, it has been decided to avoid complex configurations that involve couplers or baluns, and design a single ended Class B or “deep†AB amplifier using dividers and combiners.
CAD Technique
The MMIC design cycle is based entirely on CAD techniques, these software’s make the design steps easier for the engineer, a preliminary design with idealized components can be done for check the capabilities of the device and architecture chosen, in this case the requirements should overfilled so a real realization could reach the desired specifications. Another advantage of using CAD techniques is the possibility to perform electromagnetic simulations that will take into account effects that the models could be ignoring. During the design process many tradeoffs should be faced and software optimization is a powerful tool to find optimal points in the behavior of the circuit or to negotiate the requirements.
For the development of this work it will be used Agilent EEsof EDA Advanced Design System (ADS) from Agilent Technologies©. This software is one of the most used and the most of the foundries including UMS provide the libraries with the corresponding models for the design including passive and active components.
Layout
Once the electrical simulation is finished and accomplishes all the requirements the work moves on the layout, even in this final stage of the design some problems could raise in demands of changed of the working circuit. Many times the elements are physical too close or there is no space for the placement of the RF and DC probes, many rules should be followed in order to generate a feasible layout.
The rules are given by the selected foundry as they control the manufacturing process and know the physical limitation in size that they can manage, basically with the layout in the CAD software a mask file is generated and this is used in the foundry to create the photolithographic masks used in the fabrication process.
Channel Temperature Model
As it was mentioned before in this work the channel temperature should never exceed 115 °C when the back side of the die operates in the range of -30 °C to 80°C. Previous works have taken care of this with thermodynamic simulations in specialized software [17] [18], it is known that this temperature is of special interest when pointing to long term reliability. Most failure mechanism caused by this high temperature have been found to respond to the Arrhenius Equation depending on the activation energy, so the life time can be predicted for an specific device as shown in the Figure 3.5 .19,
Figure 3.5.19 Lifetime over temperature for a device with 1.000.000 hour median life at 150 °C[19]
With this important effect on the reliability there is a big interest in the prediction of this temperature, Ali Mohamed Darwish [1] presents a closed form expression for the thermal resistance of multifinger FET structures. The model has been tested against FEM and MoM (Method of Moments) simulators showing very good agreement with an accuracy of 2%. The thermal resistance can be calculated as:
( 3.5.0)
Where
The dimensions and are according the Figure 3.5 .20 and k corresponds to the thermal conductivity of the substrate. The temperature of the channel is therefore
( 3.5.0)
Where P is the total dissipated power.
Figure 3.5.20 FET and Gate dimensions [1]
It is important to note that the thermal conductivity k is temperature dependent and so a Kirchoff’s transformation should be applied, it can be done using the equation ( 3.5 .0) for GaAs, when it is introduced to the result in( 3.5 .0) it gives the final channel temperature ( 3.5 .0)
( 3.5.0)
( 3.5.0)
Experimentally is very difficult to measure the temperature exactly under the gate and is important to understand how the temperature changes with distance away from the channel. Given a channel temperature Tc is possible to calculate the temperature after a displacement d/2 from the channel as:
( 3.5.0)
This close expression can be added analytical to the CAD technique used in the design to include the thermal requirement in the circuit optimization, what give a big advantage and save time during the design cycle.
MMIC Amplifier Design
Design Approach
Matching Networks
Simulation results
Layout
Discrete Amplifier Design
Components Selection
Design Approach
Simulation Results
Implementation
Measurements
Conclusions and Future Fork
Conclusions
Future Work
Acknowledgments
