Investigation Of Pillar Thickness Variation Effect On Oblique Rotating Implantation (ORI)-Based Vertical Double Gate MOSFET
Introduction
Recent development of integrated circuit reveals that several fabrication aspects are already approaching the limit, especially when the dimensions are of nanometer scale . Furthermore, the complexity of lithography for nanoscale technology poses major technological challenge and skyrocketing manufacturing investment. In dealing with this issue, some innovative structures for further scaling of nanoscale devices have been elaborated, and the vertical metal oxide semiconductor field effect transistor (MOSFET) is identified as one of them. The benefits of applying vertical structure in the nanoscale era have been promoted by a number of researchers, e.g. . For ultra short channel length, the channel region could be produced with relaxed lithography in vertical architecture, instead of using complicated lithography tools for planar structure. It can handle the lithography-bounded problem in further scaling by converting the lithography process into layer definition/ deposition process for adjusting the channel length. Moreover, as the active area are located at the silicon pillar side wall, it is easier to produce double or multiple gate structure on vertical geometry with self-aligned features than on conventional/lateral geometry, that subsequently increase the drive current. It is also possible to increase the space density as the vertical structure requires less space than its planar counterpart, depending on the application.
Various methods have been proposed for developing nanometer-sized vertical structure. A number of fabrication techniques have been elaborated; either by layer epitaxy [9-11] or by silicon pillar etch combined with ion implantation methods . Epitaxy method seems to be an easier way to define the channel region vertically, but it faces difficulties in manufacturing for different type of grown layer in N- and P-type MOS. Conventional ion implantation method allows the CMOS-compatible processing; however the formation of direct vertical channel at sidewall was limited by either the silicon pillar height itself or by the nitride spacer thickness which is applied as a mask for sidewall region, which eventually creates L-shaped channel . This shape of channel leads to corner effect in the bottom of pillar, which eventually degrades the device's performance . Moreover, parasitic overlap capacitance problem is commonly found in vertical structure that provides additional effect on short channel effect (SCE). The use of fillet local oxidation (FILOX) technique above source/drain region was introduced to reduce the problem [18]. Subsequently this work was enhanced by others such as by incorporating dielectric pocket [19] or by introducing ORI method. Applying dielectric pocket may reduce short channel effect, but the possibility of further shrinkage in pillar dimension is very limited due to the presence of dielectric in the middle of pillar's top area. The later, combined with FILOX technique, was convincingly improving the channel scaling with self-aligned feature and straight vertical current (as illustrated in Fig. 1(b)) while keeping the parasitic capacitance low, and offers good short channel effect control. However, the pillar thickness in previous report is noticeably large, and its pillar shrinkage effect has not been elaborated further. In the trend of increased density for overall chip, the pillar width tends to be made in smaller dimension, thus it is of importance to investigate the effect of pillar thickness variation, especially on the fully depleted case.
In this paper, the effect of silicon pillar thickness variation on vertical double gate MOSFET with FILOX and ORI method is investigated numerically. The effect of processing variation is elaborated as well as the possibility of formation of partially- and fully-depleted device using this method, as an extension of previous work. The device's electrical characteristic and its respective subthreshold behaviour are also elaborated to understand the device performances, especially in the very short channel.
Device Simulation
The proposed vertical MOSFET structure has the feature of symmetrical self-aligned source/drain region for both gates and exhibits straight vertical channel on the sidewall, . The ORI method is employed to reveal this unique feature of the device structure. A <100> silicon wafer with uniform boron doping of 1x1019 cm-3 is selected as base substrate. This relatively high substrate doping gives benefit for the suppression of short channel effect. The silicon pillar is formed by dry etch of substrate which is selectively covered by nitride as etch mask, with the width of nitride equal to the pillar thickness tsi. In addition, the channel length definition is affected by the height of pillar.
Stress relief oxide of 20nm is thermally grown over all silicon surface, followed by the deposition of nitride layer, which subsequently is dry-etched anisotropically to define the active area. Later, a thermal oxidation process is held to produce FILOX in area which is not protected by the nitride spacers; those are the whole active area and on the top of the pillar.
The self-aligned source and drain region are constructed by arsenic implantation (6x1015 cm2, 150 keV) using Oblique Rotating Implantation (ORI) method. This method has shown a better shape of source region in the bottom, with the drain-to-source current flowing in pure vertical direction, rather than with non-ORI method. After etching of nitride spacers and stress relief oxide underneath, a 3-nm silicon oxide layer is grown on the sidewall of pillar as a gate dielectric. Later, polysilicon with in-situ As doping is deposited for gate electrode. Polysilicon spacer is patterned using dry etch, forming double gate structure with self-aligned features. After deposition of LTO for isolation, rapid thermal annealing (RTA, 11000C, 10 s) is carried out for dopant activation. Following the contact opening process, aluminum is deposited as metal contact at source and drain.
The electrical characteristics of the device were obtained by simulating the final structure using Silvaco's Atlas software package [22]. Heavy mesh was exploited especially for critical region such as gate oxide, impurity junction and channel region. The Drift-Diffusion transport model with the Boltzmann carrier transport framework was used extensively, as it is able to predict double gate MOSFET characteristic realistically , while SRH (Shockley-Read-Hall) Recombination with fixed carrier lifetimes models was selected. The Lombardi CVT model was applied as its semi-empirical equation gave the complete correlation between carrier concentration, carrier mobility, electric field and temperature for non-planar device, one which is this vertical device. Moreover, the combination of Gummel and Newton numerical methods was employed for a better initial guess in solving quantities for obtaining a convergence of the device structure.
The process simulation was calibrated by comparing the simulated and experimental results from Ref. of the 125-nm channel length vertical structure fabricated without the ORI method, as shown in Fig. 2. The figure shows good agreement between the simulated and experimental results which clearly indicate of the fact that the simulation process and the parameters used are justified.
For the purpose of investigating the channel and junction depth caused by variation of pillar dimension, the silicon thickness and height were varied. Several devices with channel length from 20 to 100 nm at various silicon thicknesses tsi (25-75 nm) were constructed and simulated. The values of pillar thickness are selected as representatives of different body potential scenarios in the pillar. The conventional vertical MOSFET (without ORI method) were used as comparison for several pillar thickness, but the channel length is limited to 50-100 nm due to recessed channel length in lateral direction at the bottom of pillar, which makes it difficult to obtain very short channel structure. In all cases, the drain is always in top of the pillar, and the backside substrate is connected to ground.
Pillar Thickness Variation And Junction Profile
Fig. 3 shows the cross section of devices with two different pillar thicknesses with different channel and source profile (tsi = 75 and 46 nm, with Lch = 40 nm and 70 nm, respectively, for Vds = 1.1 V) after all processing sequences were completely done. The current direction in channel area is purely vertical from drain to source for both cases, as the result of the source region overlapping the corner side of pillar in bottom area. This feature is of a great advantage in applying ORI method; with conventional implantation technique it is likely that the channel area become L-shape, which is the case of some reported devices (e.g.) as a consequence that the implanted doping for source region cannot occupy the pillar's corner at the bottom.
But the junction profile inside the pillar changes its shape when the pillar is made thinner, according to the source region boundary in relation with the pillar's corner. For device with tsi = 75 nm (Fig. 3(a)), the source region at the right and left side are separately formed, and the pillar region's channel area is tied to the substrate. The channel region is connected to and has the same potential with substrate, similar to bulk transistor. Meanwhile, while smaller pillar thickness is chosen (tsi= 46 nm for Fig. 3(b)), both source parts will eventually join together and forming single region, thus the pillar region become disconnected from substrate. Thus, for lower thickness, the pillar region is separated from substrate by the source region and is not tied to any potential, and floating body was created. This floating body in turn could be a disadvantage for the device performance, as it may reduce the output resistance and creating parasitic transistor on it, which is the case in the partially-depleted silicon-on-insulator (SOI) MOSFET . The transition width between body-tied and floating body of channel area in pillar depends on several factors, e.g. implantation doses, dielectric thickness and substrate doping, which requires optimization for distinct process recipes. In this research, we found that the floating body occurs for pillar thickness below 75 nm, and partially depleted channel is formed. Moreover, when the thickness of the pillar is made thinner, less than 25 nm, it turns out to be fully depleted.
The electron-hole concentration as well as potential distribution along the channel is shown in Fig. 4. At tsi = 57 nm, majority carrier in the middle of pillar region are hole, with almost as many concentration (~1018-1019 cm-3) as those at the pillar's substrate, which has same type of impurity (p-type). The collection of carriers in the middle area of pillar creates an island (as big as 50 nm in diameter at Lch = 100 nm) surrounded by the region whose majority carrier is already depleted; some literatures called this island as “depletion isolation” region . In decreased pillar thickness, the depletion isolation size is reduced as well as its peak carrier concentration. Furthermore, at tsi = 46 nm, the hole concentration in the pillar's middle region is overpowered by electron (107 to 1012 cm-3), while in tsi =36 nm, the electron concentration has almost similar concentration with the initial substrate impurities in many parts of the pillar. In addition, the depletion isolation is undetected from the graph for this thickness, while the potential barrier between drain and source exhibit very low barrier created at lowest tsi. Moreover, the behaviour at pillar thickness of 25 nm (not shown) represent the condition of fully depleted device, as is noted by the calculation of depletion width wd for respective pillar thickness . This low potential barrier explains the high current drive capability on lower pillar thickness, which the carriers flow easily without significant barrier when the channel starts conducting.
Result And Discussion
The electrical performance for different channel lengths from 100-20 nm is analyzed for several pillar thickness. The vertical ORI MOSFET shows lower threshold voltage than its conventional counterpart at every channel length for particular pillar thickness, which is the direct result of straight channel geometry. The conventional vertical structure lack the gate control in the corner region, thus preventing the quick conversion into inversion. In addition, the lower threshold is advantageous for the concern of power consumption and higher electric field in conduction state. The threshold voltage decrease is observed on shorter channel for both structures, but with tendency of more rapid decline for conventional vertical MOSFET which need to be avoided for better short channel effect control.
The pillar thickness variation effect on drain induced barrier lowering (DIBL) is shown in Fig. 6. The DIBL is calculated for threshold voltages taken at VD = 0.1 V and 1.0 V. The floating body effect (FBE) is emerged as shown by increasing DIBL value on pillar narrowing, especially in partially depletion (PD) at thickness of 57nm and 46 nm before falling down again to fully depleted (FD) feature. This effect appears irrelevant for conventional vertical structure which has the propensity to decreasing DIBL for smaller tsi. The appearance of isolated area at PD regime in the middle of the pillar is believed to provide injection of majority carrier in the area (i.e. hole) to the body comparable to the drain bias (also found similarly in the PD silicon on insulator), which later shift down the threshold voltage at larger bias and creates large discrepancy with threshold voltage at low drain voltage. With the reduction of pillar thickness toward FD regime, the isolated island is gradually diminished and its unwanted effect is effectively suppressed; the channel control by both gates is stronger than the drain, thus result in the low DIBL.
exhibits sub-threshold swing (S) on the variation of channel length at several pillar thickness, which shows that the swing is decreased for smaller pillar thickness, both with ORI and non-ORI method. Furthermore, the swing gets closer to ideal value (i.e. 60 mV/decade for bulk structure) for ORI method, especially for large channel. The increase of substhreshold swing in ultra short channel is evident for all pillar thickness for both methods, but with steeper increase in non-ORI method. The swing reduction in ORI-based vertical MOSFET for the same channel length indicates an increase in gate-gate charge coupling with a decreasing pillar thickness. On the other hand, conventional vertical device suffers from high swing due to less control of gate near the corner.
It is found that drain current of ON-state, IDon, calculated at VD=2V and Vg - VT = 1V, rises for smaller pillar thickness, especially when it is close to fully depletion and also for smaller channel length, as shown in Fig. 8. Furthermore, Fig. 9 reveals that the leakage current, calculated at Vg= 0 V, tend to increase in the reduction of pillar thickness and channel length. A caution must be taken for the higher leakage current which could lead to rise in power consumption, as the power needed in 'off' state will be significantly high. On the other hand, the conventional vertical device has lower ON current than the ORI method, due to the fact that the change of direction of current at the pillar corner alters the effective mobility of the charge, which in turn reduces the total current, the phenomenon which is successfully eliminated by the ORI method.
Based from our evaluation above, the vertical ORI method gives better prospect in further scaling of MOSFET than its conventional counterpart while it still maintain the compatibility with standard processing. Moreover, in the future application, it is more advantageous to switch to fully depleted pillar as it shows better overall performance than in partially depleted structure, although the issue of producing reliable ultra thin pillar is of concern that must be answered.
Conclusion
The structure of vertical double gate MOSFET fabricated with ORI method has been numerically simulated and studied for silicon pillar thicknesses from 75-25 nm, which ranges from body-tied to partially-depleted to fully-depleted channel. The electrical performance for channel length variation between 100-20 nm have also been analyzed. It has been demonstrated that the vertical devices using ORI method shows generally better performance in terms of lower sub-threshold swing, DIBL and threshold roll-off and higher drive current than the conventional implantation vertical device for all pillar thickness. This improvement is best explained due to the elimination of corner effect that degrades the gate control and decreases the effective mobility. Shrinking down the silicon pillar thickness below 75 nm eventually creates floating body when the source area from each gate merges in the bottom of pillar. The reduction of pillar thickness produces the decline in threshold voltage and subthreshold swing for the same channel length, but the presence of isolated depletion region in the middle of pillar at floating body increases parasitic effect for higher Vds, which is evident in higher DIBL. By further reduction of pillar thickness towards fully depleted feature (i.e. less than 25 nm in this case), the increasing gate-to gate charge coupling improves the performance of ORI-based vertical double gate MOSFET, as evident in near-ideal swing value, lower DIBL and better current drive, compared to the partially-depleted and body-tied device.
Acknowledgment
The authors would like to thank the Malaysia Ministry of Science, Technology and Innovation (MOSTI) for sponsoring this work under E-Science Fund, and the Research Management Centre of UTM for providing invaluable assistance in conducting the research.
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