Abstract- This paper deals with different kinds of mismatches that are observed in analog integrated circuits. Section I gives an idea of the systematic, random mismatch and their sources. Section II of the paper discusses the impact of mismatch on the design and yield of the circuits. Section III of the paper gives some methodologies to reduce the effect of mismatch in integrated circuits.
I. Introduction
Small random variations occur during the manufacturing of circuit devices, resulting in behavioral differences between identically designed devices. These variations are known as device mismatches or circuit non-idealities. In general, mismatch can be classified into two categories according to the different generating mechanisms: fabricated-related mismatch and ambient-related mismatch. For the fabricated-related mismatch, there are two more detailed categories: systematic mismatch and random mismatch. The systematic component of the mismatch represents that portion of the mismatch which can be precisely predicted, given the process gradients. The random mismatch, on the contrary, represents that portion of the mismatch which is stochastic and hence cannot be predicted.
The presence of process gradients causes systematic mismatch in the parameter value of the device. Some of the sources of systematic mismatch are variations in gate dimensions, gate-oxide thickness gradients, variations in channel doping, and source/drain asymmetry, such as introduced by the tilt angle of ion implants. Systematic effects are important for large distances, but appropriate layout techniques can minimize them.
Random mismatch refers to local variation in parameters such as doping concentration, mobility, oxide thickness, and polysilicon granularity. Random mismatch dominates systematic mismatch for short distances and is generally assumed to display a Gaussian distribution characterized by the random mismatch's standard deviation.
II Impact of mismatch
A. Impact on Design
In general, there are two variations to consider in an integrated circuit process. Global variation accounts for the total variation in the value of a component over a wafer or a batch. Local variation or mismatch reflects the variation in a component value with reference to an adjacent component on the same chip. The design of precision analog circuits is based on component ratios rather than their absolute values. The characterization of mismatch in MOS transistors is more complex than that in the case of capacitors. The drain current matching not only depends on the device dimensions but also on the operating point. Generally, MOS transistors will be operating in the saturation region in analog circuits. Therefore we should relate the measured mismatches in V_T and K to the saturation region, where the drain current is given by I=K/2 (V_GS-V_T )^2. Then the variance in the drain current may be written as (s_I^2)/'^2 =(s_K^2)/?^2 +4(s_VT^2)/(V_GS-?_T )^2 -4r.s_VT/(V_GS-?_T ).s_K/?
Here r is the correlation coefficient between the mismatches in V_T and ?, ? is the expected value of the random variable I,s_I is the standard deviation of I and so on. Thus the mismatch in drain current at any operating point may be estimated if s_k,s_VTand r are known. The standard deviation of K is given by s_K=[1/(N-1) {?_(i=1)^n'??_KT?^2 -1/N (?_(i=)^n'?_KT )^2 } ]^(1/2) where N is the number of matched pairs measured on each wafer.
The nonuniform distribution of the dopant atoms in the bulk is a major contributor to the threshold voltage mismatch. Devices which use a compensating threshold adjust implant have a higher mismatch in threshold voltage due to the differential doping occurring at the surface. This is the major reason for the significantly larger mismatch noticed in p-channel devices as compared to n-channel transistors.
The gate oxide capacitance is quite uniform and hence has little influence on the threshold voltage mismatch. The mismatch in K due to edge variations is proportional to? (1/L^2 +1/W^2 )?^(1/2). The standard deviation of mismatch in length and width is in the range 0.01'0.03 pm. For n-channel devices, this is the dominant source of mismatch in K and the variation in mobility has little effect on the mismatch in K. The corresponding quantity for p-channel transistors, however, could be larger due to any damage in substrate caused by threshold voltage implant. A common contributing factor to the mismatches in VT and K is the variation in the gate oxide capacitance.
B. Impact on Yield definition
The scaling of feature size has progressed more rapidly than the scaling of process tolerances, so that the statistical variations of device characteristics can be very significant. Thus, if a circuit was designed to achieve specific nominal values of performances, a dispersion of actual performances can be expected in a population of manufactured chips. A manufactured circuit will be considered acceptable if it works properly, i.e., if it works and all of its actual performances fall within acceptable bounds, which define the 'region of acceptability.' Defects that may cause yield loss are usually categorized as fatal random defects (or faults) and parametric irregularities. The former, such as short circuits between conductors or pinholes in the insulator, often cause circuit to malfunction. The latter, such as random variations of oxide thickness in an MOS transistor, do not generally cause catastrophic circuit failures but may degrade circuit performances. Therefore, chip yield can be seen as the product of the fraction of chips that is free of fatal random defects (referred to as defect or functional yield) by the fraction of chips that is free of parametric irregularities which cause circuit performances to be unacceptable (referred to as parametric yield) Parametric yield is more easily controlled by designers than defect yield by adjustments of the device dimensions and placements, provided that accurate parametric variation models are available. Because of the close correlation between high yield and high profits, it is essential for IC manufacturers to maximize yield. For this reason, statistical design techniques and suitable CAD tools are necessary to design IC's with maximum yield on the other hand, statistical modeling can identify the least critical parameters, i.e., those for which tolerances have minor effects on the dispersion of performances. This may allow less expensive processing steps or simpler circuit topologies to be used, thus, reducing manufacturing cost.
III Techniques to minimize mismatches
A. Layout Techniques
Process variation during fabrication may limit accuracy and desired performance of analog circuits and hence matching between components in layout of analog circuits is an important issue in many designs. Layout techniques are effectively used to minimize first-order mismatch errors due to variations in these process parameters: gate-oxide thickness, lateral diffusion, oxide encroachment, and oxide charge density.
Good layout practices for analog circuits include the following
1) Use gate lengths several times larger than the technology's minimum gate length if all possible. This helps reduces ? effects while improving matching.
2) Use multiple source/drain contacts along the width of the transistor to reduce parasitic resistance and provides evenly distributed current through the device. This is shown in figure1.
3) Interdigitize large aspect ratio devices to reduce source/drain depletion capacitance. Using an even number (n) of gate fingers can reduce Cdb, Csb by one-half or (n + 2)/2n depending on source/drain designation. Typically it is preferred to reduce drain capacitance more so than source capacitance. Also use dummy poly strips to minimize mismatch induced by etch undercutting during fab. This process is illustrated in figure 2.
4) Matched devices should have identical orientation. An example of what not to do is shown below.
5)Interdigitization and Common Centroid Techniques: Interdigitization can be used in a multiple transistor circuit layout to distribute process gradients across the circuit. This improves matching. Suppose we have to match two components A and B (A and B can be anything like capacitor, resistor or transistor). Lets split A and B into 4 small components i.e. A1-A4 and B1-B4. The inter digitization technique is as shown in figure 4.
The Common Centroid layout technique reduces systematic gradients when compared to simple and interdigitized techniques.In the interdigitization technique the components are placed alternately where as in the common centroid the components are placed such that they have a common centroid. This technique is as shown in figure 5.
B. Design Techniques
Device mismatch limits the accuracy of circuits and has important implications on the offsets of operational amplifiers or comparators, on the bit accuracy of AID and DIA convertors, and on the power supply- noise and common-mode rejection ratio's in differential structures. The accuracy performance can be increased in two ways: the matching of devices is improved by increasing the device size, or auto-zero and offset compensation techniques are used to reduce the effect of mismatches on the system performance. The compensation techniques require calibration phases during which the normal system operation is interrupted and the offsets of the building blocks are sampled and dynamically stored in an analog memory circuit. In many high speed analog signal processing systems the interruptions of the operation of the system cannot be tolerated or the required continuous operation phases are too long. Therefore compensation techniques are not applicable and the accuracy performance of the system completely depends on the matching quality of the technology. To improve the system accuracy, large devices have to be used so that the capacitive loading of the circuit nodes increases and more power is required to attain a certain speed performance. As a result, the matching quality of the technology has a direct impact on the minimal power consumption of high precision building blocks. During the design of a MOS circuit the designer has to choose the current, width and length of the devices. For a given current and bias point, only the aspect ratio of the device is fixed, but the width or the length can still be chosen freely. The use of shorter channel devices helps to reduce the capacitive load in the circuit. This results in lower power consumption for a given bandwidth or operation frequency and a reduction in the power-bandwidth ratio. However, due to device mismatch there is a minimal required device area to achieve a given dc accuracy. This introduces an additional constraint that fixes the minimal area and thus circuit capacitance. In a given analog integrated circuit threshold voltage plays an important role in determining the total accuracy of the circuit. To attain high speed and reduce the effects of threshold voltage mismatch, a large gate over drive voltage should be used. The transconductance is a process parameter and as the CMOS scales downwards the mismatch due to oxide variations and mobility differences might get better. However, there is less averaging of these variations with the smaller layout sizes. One aspect that is critical for generating accurate currents is the drain to source voltage. It is extremely important for good matching that the drain to source voltages of the MOSFET'S in the circuit are equal.
C. Calibration Technique
The performance of a device is degraded by mismatches in the transfer characteristics of the component. These mismatches include offset, gain, and aperture mismatches that would not limit linearity without interleaving. Trimming or calibration are traditionally used to overcome this problem. Trimming has the advantage of being transparent to the user but the disadvantage of being unable to track variations over time. On the other hand, while calibration can be used to track variations over time, traditional calibration techniques are applied in the foreground; that is, the calibration interrupts the conversion of the input. Foreground calibration is inconvenient and cannot be used in applications where the device is always in service. Also, calibration in the foreground may generate interference that disappears during normal device operation, resulting in calibration errors.
A self-calibration technique is used to realize an array of current sources which are equal to each other within 0.02 percent. The calibration of a MOS current source is done by biasing it with a reference current. After that, the gate is disconnected from the biasing circuit and since the gate-to-source voltage is not changed, the value of the output current of the current source equals the reference value. To reduce the sensitivity for clock feed through in switches and for diode leakage currents, calibration is done only on the difference between a main current source and the reference current. The array of calibrated sources is extended with a spare source to ensure that enough calibrated currents are available at any time. The technique can be used in any application that requires equal currents.
IV Conclusion
Different types of mismatches in analog integrated circuits are discussed. The impact of these mismatches on the performance of the circuit is explained in detail. The mismatches impose certain limitations on the design and also effect the yield. Various methodologies have been discussed to overcome the mismatch effects on the circuit. The layout method aims at eliminating the first order mismatches, design method aims at improving the accuracy of the circuit and calibration method is used to over come non linearities due to offset, gain and aperture mismatches.
